SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Table 18-2 lists the memory-mapped registers for the CMPSS_REGS registers. All register offset addresses not listed in Table 18-2 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | COMPCTL | CMPSS Comparator Control Register | EALLOW | Go |
1h | COMPHYSCTL | CMPSS Comparator Hysteresis Control Register | EALLOW | Go |
2h | COMPSTS | CMPSS Comparator Status Register | Go | |
3h | COMPSTSCLR | CMPSS Comparator Status Clear Register | EALLOW | Go |
4h | COMPDACCTL | CMPSS DAC Control Register | EALLOW | Go |
6h | DACHVALS | CMPSS High DAC Value Shadow Register | Go | |
7h | DACHVALA | CMPSS High DAC Value Active Register | Go | |
8h | RAMPMAXREFA | CMPSS Ramp Max Reference Active Register | Go | |
Ah | RAMPMAXREFS | CMPSS Ramp Max Reference Shadow Register | Go | |
Ch | RAMPDECVALA | CMPSS Ramp Decrement Value Active Register | Go | |
Eh | RAMPDECVALS | CMPSS Ramp Decrement Value Shadow Register | Go | |
10h | RAMPSTS | CMPSS Ramp Status Register | Go | |
12h | DACLVALS | CMPSS Low DAC Value Shadow Register | Go | |
13h | DACLVALA | CMPSS Low DAC Value Active Register | Go | |
14h | RAMPDLYA | CMPSS Ramp Delay Active Register | Go | |
15h | RAMPDLYS | CMPSS Ramp Delay Shadow Register | Go | |
16h | CTRIPLFILCTL | CTRIPL Filter Control Register | EALLOW | Go |
17h | CTRIPLFILCLKCTL | CTRIPL Filter Clock Control Register | EALLOW | Go |
18h | CTRIPHFILCTL | CTRIPH Filter Control Register | EALLOW | Go |
19h | CTRIPHFILCLKCTL | CTRIPH Filter Clock Control Register | EALLOW | Go |
1Ah | COMPLOCK | CMPSS Lock Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 18-3 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
COMPCTL is shown in Figure 18-7 and described in Table 18-4.
Return to the Summary Table.
CMPSS Comparator Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
COMPDACE | ASYNCLEN | CTRIPOUTLSEL | CTRIPLSEL | COMPLINV | COMPLSOURCE | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ASYNCHEN | CTRIPOUTHSEL | CTRIPHSEL | COMPHINV | COMPHSOURCE | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | COMPDACE | R/W | 0h | Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled Reset type: SYSRSn |
14 | ASYNCLEN | R/W | 0h | Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with latched digital filter output 1 Asynchronous comparator output feeds into OR gate with latched digital filter output Reset type: SYSRSn |
13-12 | CTRIPOUTLSEL | R/W | 0h | Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives CTRIPOUTL Reset type: SYSRSn |
11-10 | CTRIPLSEL | R/W | 0h | Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL Reset type: SYSRSn |
9 | COMPLINV | R/W | 0h | Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted Reset type: SYSRSn |
8 | COMPLSOURCE | R/W | 0h | Low comparator input source. 0 Inverting input of comparator driven by internal DAC 1 Inverting input of comparator driven through external pin Reset type: SYSRSn |
7 | RESERVED | R | 0h | Reserved |
6 | ASYNCHEN | R/W | 0h | High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with latched digital filter output 1 Asynchronous comparator output feeds into OR gate with latched digital filter output Reset type: SYSRSn |
5-4 | CTRIPOUTHSEL | R/W | 0h | High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives CTRIPOUTH Reset type: SYSRSn |
3-2 | CTRIPHSEL | R/W | 0h | High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH Reset type: SYSRSn |
1 | COMPHINV | R/W | 0h | High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted Reset type: SYSRSn |
0 | COMPHSOURCE | R/W | 0h | High comparator input source. 0 Inverting input of comparator driven by internal DAC 1 Inverting input of comparator driven through external pin Reset type: SYSRSn |
COMPHYSCTL is shown in Figure 18-8 and described in Table 18-5.
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CMPSS Comparator Hysteresis Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMPHYS | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3-0 | COMPHYS | R/W | 0h | Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others : undefined Reset type: SYSRSn |
COMPSTS is shown in Figure 18-9 and described in Table 18-6.
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CMPSS Comparator Status Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COMPLLATCH | COMPLSTS | |||||
R-0h | R-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMPHLATCH | COMPHSTS | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9 | COMPLLATCH | R | 0h | Latched value of low comparator digital filter output Reset type: SYSRSn |
8 | COMPLSTS | R | 0h | Low comparator digital filter output Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | COMPHLATCH | R | 0h | Latched value of high comparator digital filter output Reset type: SYSRSn |
0 | COMPHSTS | R | 0h | High comparator digital filter output Reset type: SYSRSn |
COMPSTSCLR is shown in Figure 18-10 and described in Table 18-7.
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CMPSS Comparator Status Clear Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LSYNCCLREN | LLATCHCLR | RESERVED | ||||
R-0h | R/W-0h | R-0/W1S-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSYNCCLREN | HLATCHCLR | RESERVED | ||||
R-0h | R/W-0h | R-0/W1S-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10 | LSYNCCLREN | R/W | 0h | Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch Reset type: SYSRSn |
9 | LLATCHCLR | R-0/W1S | 0h | Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH] Reset type: SYSRSn |
8-3 | RESERVED | R | 0h | Reserved |
2 | HSYNCCLREN | R/W | 0h | High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch Reset type: SYSRSn |
1 | HLATCHCLR | R-0/W1S | 0h | High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH] Reset type: SYSRSn |
0 | RESERVED | R | 0h | Reserved |
COMPDACCTL is shown in Figure 18-11 and described in Table 18-8.
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CMPSS DAC Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FREESOFT | RESERVED | BLANKEN | BLANKSOURCE | ||||
R/W-0h | R-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWLOADSEL | RAMPLOADSEL | SELREF | RAMPSOURCE | DACSOURCE | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | FREESOFT | R/W | 0h | Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER during emulation suspend 1Xb Ramp generator runs freely Reset type: SYSRSn |
13 | RESERVED | R | 0h | Reserved |
12 | BLANKEN | R/W | 0h | EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled. Reset type: SYSRSn |
11-8 | BLANKSOURCE | R/W | 0h | EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK ... n-1 EPWMnBLANK Reset type: SYSRSn |
7 | SWLOADSEL | R/W | 0h | Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER Reset type: SYSRSn |
6 | RAMPLOADSEL | R/W | 0h | Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS Reset type: SYSRSn |
5 | SELREF | R/W | 0h | DAC reference select. Determines which voltage supply is used as the reference for the internal comparator DACs. 0 VDDA is the voltage reference for the DAC 1 VDAC is the voltage reference for the DAC Reset type: SYSRSn |
4-1 | RAMPSOURCE | R/W | 0h | EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2 EPWM3SYNCPER ... n-1 EPWMnSYNCPER Reset type: SYSRSn |
0 | DACSOURCE | R/W | 0h | DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator Reset type: SYSRSn |
DACHVALS is shown in Figure 18-12 and described in Table 18-9.
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CMPSS High DAC Value Shadow Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DACVAL | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DACVAL | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11-0 | DACVAL | R/W | 0h | High DAC shadow value. When COMPDACCTL[DACSOURCE]=0, the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]. Reset type: SYSRSn |
DACHVALA is shown in Figure 18-13 and described in Table 18-10.
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CMPSS High DAC Value Active Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DACVAL | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DACVAL | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11-0 | DACVAL | R | 0h | High DAC active value. Value that is actively driven by the high DAC. Reset type: SYSRSn |
RAMPMAXREFA is shown in Figure 18-14 and described in Table 18-11.
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CMPSS Ramp Max Reference Active Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMPMAXREF | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMPMAXREF | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RAMPMAXREF | R | 0h | Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS. Reset type: SYSRSn |
RAMPMAXREFS is shown in Figure 18-15 and described in Table 18-12.
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CMPSS Ramp Max Reference Shadow Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMPMAXREF | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMPMAXREF | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RAMPMAXREF | R/W | 0h | Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS. Reset type: SYSRSn |
RAMPDECVALA is shown in Figure 18-16 and described in Table 18-13.
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CMPSS Ramp Decrement Value Active Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMPDECVAL | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMPDECVAL | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RAMPDECVAL | R | 0h | Ramp decrement value active. Latched value that will be subtracted from RAMPSTS. Reset type: SYSRSn |
RAMPDECVALS is shown in Figure 18-17 and described in Table 18-14.
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CMPSS Ramp Decrement Value Shadow Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMPDECVAL | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMPDECVAL | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RAMPDECVAL | R/W | 0h | Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA. Reset type: SYSRSn |
RAMPSTS is shown in Figure 18-18 and described in Table 18-15.
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CMPSS Ramp Status Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RAMPVALUE | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMPVALUE | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | RAMPVALUE | R | 0h | Ramp value. Present value of ramp generator. Reset type: SYSRSn |
DACLVALS is shown in Figure 18-19 and described in Table 18-16.
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CMPSS Low DAC Value Shadow Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DACVAL | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DACVAL | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11-0 | DACVAL | R/W | 0h | Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]. Reset type: SYSRSn |
DACLVALA is shown in Figure 18-20 and described in Table 18-17.
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CMPSS Low DAC Value Active Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DACVAL | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DACVAL | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11-0 | DACVAL | R | 0h | Low DAC active value. Value that is actively driven by the low DAC. Reset type: SYSRSn |
RAMPDLYA is shown in Figure 18-21 and described in Table 18-18.
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CMPSS Ramp Delay Active Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DELAY | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DELAY | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12-0 | DELAY | R | 0h | Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received. Reset type: SYSRSn |
RAMPDLYS is shown in Figure 18-22 and described in Table 18-19.
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CMPSS Ramp Delay Shadow Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DELAY | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DELAY | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12-0 | DELAY | R/W | 0h | Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA. Reset type: SYSRSn |
CTRIPLFILCTL is shown in Figure 18-23 and described in Table 18-20.
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CTRIPL Filter Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FILINIT | RESERVED | THRESH | SAMPWIN | ||||
R-0/W1S-0h | R-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SAMPWIN | RESERVED | ||||||
R/W-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | FILINIT | R-0/W1S | 0h | Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value Reset type: SYSRSn |
14 | RESERVED | R | 0h | Reserved |
13-9 | THRESH | R/W | 0h | Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1. Reset type: SYSRSn |
8-4 | SAMPWIN | R/W | 0h | Low filter sample window size. Number of samples to monitor is SAMPWIN+1. Reset type: SYSRSn |
3-0 | RESERVED | R | 0h | Reserved |
CTRIPLFILCLKCTL is shown in Figure 18-24 and described in Table 18-21.
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CTRIPL Filter Clock Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKPRESCALE | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKPRESCALE | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | CLKPRESCALE | R/W | 0h | Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1. Reset type: SYSRSn |
CTRIPHFILCTL is shown in Figure 18-25 and described in Table 18-22.
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CTRIPH Filter Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FILINIT | RESERVED | THRESH | SAMPWIN | ||||
R-0/W1S-0h | R-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SAMPWIN | RESERVED | ||||||
R/W-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | FILINIT | R-0/W1S | 0h | High filter initialization. 0 No effect 1 Initialize all samples to the filter input value Reset type: SYSRSn |
14 | RESERVED | R | 0h | Reserved |
13-9 | THRESH | R/W | 0h | High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1. Reset type: SYSRSn |
8-4 | SAMPWIN | R/W | 0h | High filter sample window size. Number of samples to monitor is SAMPWIN+1. Reset type: SYSRSn |
3-0 | RESERVED | R | 0h | Reserved |
CTRIPHFILCLKCTL is shown in Figure 18-26 and described in Table 18-23.
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CTRIPH Filter Clock Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKPRESCALE | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKPRESCALE | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | CLKPRESCALE | R/W | 0h | High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1. Reset type: SYSRSn |
COMPLOCK is shown in Figure 18-27 and described in Table 18-24.
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CMPSS Lock Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CTRIP | DACCTL | COMPHYSCTL | COMPCTL | ||
R-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | CTRIP | R/WSonce | 0h | Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL* registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL* registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL* registers are locked. Only a system reset can clear this bit. Reset type: SYSRSn |
2 | DACCTL | R/WSonce | 0h | Lock write-access to the COMPDAC*CTL* register(s). 0 COMPDAC*CTL* register(s) not locked. Write 0 to this bit has no effect. 1 COMPDAC*CTL* register(s) locked. Only a system reset can clear this bit. Reset type: SYSRSn |
1 | COMPHYSCTL | R/WSonce | 0h | Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit. Reset type: SYSRSn |
0 | COMPCTL | R/WSonce | 0h | Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit. Reset type: SYSRSn |