SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Table 3-211 lists the memory-mapped registers for the PERIPH_AC_REGS registers. All register offset addresses not listed in Table 3-211 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | ADCA_AC | ADCA Master Access Control Register | EALLOW | Go |
2h | ADCB_AC | ADCB Master Access Control Register | EALLOW | Go |
4h | ADCC_AC | ADCC Master Access Control Register | EALLOW | Go |
10h | CMPSS1_AC | CMPSS1 Master Access Control Register | EALLOW | Go |
12h | CMPSS2_AC | CMPSS2 Master Access Control Register | EALLOW | Go |
14h | CMPSS3_AC | CMPSS3 Master Access Control Register | EALLOW | Go |
16h | CMPSS4_AC | CMPSS4 Master Access Control Register | EALLOW | Go |
28h | DACA_AC | DACA Master Access Control Register | EALLOW | Go |
2Ah | DACB_AC | DACB Master Access Control Register | EALLOW | Go |
48h | EPWM1_AC | EPWM1 Master Access Control Register | EALLOW | Go |
4Ah | EPWM2_AC | EPWM2 Master Access Control Register | EALLOW | Go |
4Ch | EPWM3_AC | EPWM3 Master Access Control Register | EALLOW | Go |
4Eh | EPWM4_AC | EPWM4 Master Access Control Register | EALLOW | Go |
50h | EPWM5_AC | EPWM5 Master Access Control Register | EALLOW | Go |
52h | EPWM6_AC | EPWM6 Master Access Control Register | EALLOW | Go |
54h | EPWM7_AC | EPWM7 Master Access Control Register | EALLOW | Go |
56h | EPWM8_AC | EPWM8 Master Access Control Register | EALLOW | Go |
70h | EQEP1_AC | EQEP1 Master Access Control Register | EALLOW | Go |
72h | EQEP2_AC | EQEP2 Master Access Control Register | EALLOW | Go |
80h | ECAP1_AC | ECAP1 Master Access Control Register | EALLOW | Go |
82h | ECAP2_AC | ECAP2 Master Access Control Register | EALLOW | Go |
84h | ECAP3_AC | ECAP3 Master Access Control Register | EALLOW | Go |
A8h | SDFM1_AC | SDFM1 Master Access Control Register | EALLOW | Go |
AAh | SDFM2_AC | SDFM2 Master Access Control Register | EALLOW | Go |
B0h | CLB1_AC | CLB1 Master Access Control Register | EALLOW | Go |
B2h | CLB2_AC | CLB2 Master Access Control Register | EALLOW | Go |
B4h | CLB3_AC | CLB3 Master Access Control Register | EALLOW | Go |
B6h | CLB4_AC | CLB4 Master Access Control Register | EALLOW | Go |
100h | SCIA_AC | SCIA Master Access Control Register | EALLOW | Go |
102h | SCIB_AC | SCIB Master Access Control Register | EALLOW | Go |
110h | SPIA_AC | SPIA Master Access Control Register | EALLOW | Go |
112h | SPIB_AC | SPIB Master Access Control Register | EALLOW | Go |
120h | I2CA_AC | I2CA Master Access Control Register | EALLOW | Go |
122h | I2CB_AC | I2CB Master Access Control Register | EALLOW | Go |
130h | PMBUS_A_AC | PMBUSA Master Access Control Register | EALLOW | Go |
138h | LIN_A_AC | LINA Master Access Control Register | EALLOW | Go |
13Ah | LIN_B_AC | LINB Master Access Control Register | EALLOW | Go |
140h | DCANA_AC | DCANA Master Access Control Register | EALLOW | Go |
148h | MCANA_AC | MCANA Master Access Control Register | EALLOW | Go |
158h | FSIATX_AC | FSIA Master Access Control Register | EALLOW | Go |
15Ah | FSIARX_AC | FSIB Master Access Control Register | EALLOW | Go |
1AAh | HRPWM_A_AC | HRPWM Master Access Control Register | EALLOW | Go |
1ACh | HIC_A_AC | HIC Master Access Control Register | EALLOW | Go |
1AEh | AESA_AC | AES Master Access Control Register | EALLOW | Go |
1FEh | PERIPH_AC_LOCK | Lock Register to stop Write access to peripheral Access register. | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-212 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
ADCA_AC is shown in Figure 3-195 and described in Table 3-213.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ADCB_AC is shown in Figure 3-196 and described in Table 3-214.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ADCC_AC is shown in Figure 3-197 and described in Table 3-215.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS1_AC is shown in Figure 3-198 and described in Table 3-216.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS2_AC is shown in Figure 3-199 and described in Table 3-217.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS3_AC is shown in Figure 3-200 and described in Table 3-218.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CMPSS4_AC is shown in Figure 3-201 and described in Table 3-219.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
DACA_AC is shown in Figure 3-202 and described in Table 3-220.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
DACB_AC is shown in Figure 3-203 and described in Table 3-221.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM1_AC is shown in Figure 3-204 and described in Table 3-222.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM2_AC is shown in Figure 3-205 and described in Table 3-223.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM3_AC is shown in Figure 3-206 and described in Table 3-224.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM4_AC is shown in Figure 3-207 and described in Table 3-225.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM5_AC is shown in Figure 3-208 and described in Table 3-226.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM6_AC is shown in Figure 3-209 and described in Table 3-227.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM7_AC is shown in Figure 3-210 and described in Table 3-228.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EPWM8_AC is shown in Figure 3-211 and described in Table 3-229.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EQEP1_AC is shown in Figure 3-212 and described in Table 3-230.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
EQEP2_AC is shown in Figure 3-213 and described in Table 3-231.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ECAP1_AC is shown in Figure 3-214 and described in Table 3-232.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ECAP2_AC is shown in Figure 3-215 and described in Table 3-233.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
ECAP3_AC is shown in Figure 3-216 and described in Table 3-234.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SDFM1_AC is shown in Figure 3-217 and described in Table 3-235.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SDFM2_AC is shown in Figure 3-218 and described in Table 3-236.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CLB1_AC is shown in Figure 3-219 and described in Table 3-237.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CLB2_AC is shown in Figure 3-220 and described in Table 3-238.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CLB3_AC is shown in Figure 3-221 and described in Table 3-239.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
CLB4_AC is shown in Figure 3-222 and described in Table 3-240.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SCIA_AC is shown in Figure 3-223 and described in Table 3-241.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SCIB_AC is shown in Figure 3-224 and described in Table 3-242.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SPIA_AC is shown in Figure 3-225 and described in Table 3-243.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
SPIB_AC is shown in Figure 3-226 and described in Table 3-244.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
I2CA_AC is shown in Figure 3-227 and described in Table 3-245.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
I2CB_AC is shown in Figure 3-228 and described in Table 3-246.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R-0-0h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
PMBUS_A_AC is shown in Figure 3-229 and described in Table 3-247.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
LIN_A_AC is shown in Figure 3-230 and described in Table 3-248.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
LIN_B_AC is shown in Figure 3-231 and described in Table 3-249.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
DCANA_AC is shown in Figure 3-232 and described in Table 3-250.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
MCANA_AC is shown in Figure 3-233 and described in Table 3-251.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | RESERVED | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | RESERVED | R/W | 3h | Reserved |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
FSIATX_AC is shown in Figure 3-234 and described in Table 3-252.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
FSIARX_AC is shown in Figure 3-235 and described in Table 3-253.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
HRPWM_A_AC is shown in Figure 3-236 and described in Table 3-254.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HICA_ACC | DMA1_ACC | CLA1_ACC | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | HICA_ACC | R/W | 3h | Defines Access control definition for the HICA as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | CLA1_ACC | R/W | 3h | Defines Access control definition for the CLA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
HIC_A_AC is shown in Figure 3-237 and described in Table 3-255.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
AESA_AC is shown in Figure 3-238 and described in Table 3-256.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected master.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMA1_ACC | RESERVED | CPU1_ACC | ||||
R/W-3h | R/W-3h | R/W-3h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-6 | RESERVED | R/W | 3h | Reserved |
5-4 | DMA1_ACC | R/W | 3h | Defines Access control definition for the DMA1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
3-2 | RESERVED | R/W | 3h | Reserved |
1-0 | CPU1_ACC | R/W | 3h | Defines Access control definition for the CPU1 as: 11: Full Access for both read and Write 10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral Reset type: XRSn |
PERIPH_AC_LOCK is shown in Figure 3-239 and described in Table 3-257.
Return to the Summary Table.
Based on status bit control the Access registers are either RD/WR or RD only.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_AC_WR | ||||||
R-0-0h | R/WSonce-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | LOCK_AC_WR | R/WSonce | 0h | Defines Access control definition for the CPU1 as: 1: Access Control registers are Read Only 0: Read/Write Access allowed to Access Control registers. Writing '1' sets the bit, writing '0' has no effect. Reset type: SYSRSn |