SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Table 4-3 describes the general boot ROM procedure each time the CPU core is reset.
During boot, boot ROM code updates a boot status location in RAM that details the actions taken during this process. Refer to Section 4.8.12 for more details.
Step | CPU Action |
---|---|
1 | After reset, check for HWBIST reset. If it is a HWBIST reset, immediately branch and return to the user application. If it is not a HWBIST reset, then continue boot and check the FUSE error register for any errors and handle accordingly. |
2 | Clock configuration and Flash power-up |
3 | Peripheral trimming and device configuration registers are loaded from OTP. |
4 | On power-on reset (POR), all RAMs are initialized. |
5 | Non-maskable interrupt (NMI) handling is enabled and DCSM initialization is performed. |
6 | Device calibration is performed; trimming the specified peripherals with set OTP values. |
7 | Determine if polling the GPIO pins are needed for determining the boot mode and, if so, read the boot mode GPIO pins to determine the boot mode to run. |
8 | Based on the boot mode and options, the appropriate boot sequence is executed. Refer to Section 4.6.1 for a flow chart of the boot sequences. |