SPRUIY5A February   2021  – July 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   Trademarks
  2. 1 Stackup
  3. 2 Floorplan Component Placement
  4. 3 Critical Interfaces Impact Placement
  5. 4 Route Critical Interfaces First
  6. 5 Route SERDES Interfaces First
  7. 6 Route DDR Signals
    1. 6.1 Address, Command, Control, and Clock Group Routes
    2. 6.2 Data Group Routes
  8. 7 Complete Power Decoupling
  9. 8 Route Lowest Priority Interfaces
  10. 9 References
  11. 10Revision History

8 Route Lowest Priority Interfaces

When the length matching and simulations have been completed for the highest priority interfaces, and the Power Distribution Network (PDN) analysis has been completed, then the layout can continue with the medium and lower priority interfaces. For additional information, refer to the Sitara™ Processor Power Distribution Networks: Implementation and Analysis.