SPRUIY5A February   2021  – July 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   Trademarks
  2. 1 Stackup
  3. 2 Floorplan Component Placement
  4. 3 Critical Interfaces Impact Placement
  5. 4 Route Critical Interfaces First
  6. 5 Route SERDES Interfaces First
  7. 6 Route DDR Signals
    1. 6.1 Address, Command, Control, and Clock Group Routes
    2. 6.2 Data Group Routes
  8. 7 Complete Power Decoupling
  9. 8 Route Lowest Priority Interfaces
  10. 9 References
  11. 10Revision History

7 Complete Power Decoupling

The middle priority interfaces and the power distribution planes and pours are routed after the SERDES and DDR interfaces. TI strongly recommends completing all SERDES and DDR routing before continuing with other interfaces. Note that the power distribution planes and pours and all of the decoupling must be placed before PCB simulations are executed for the SERDES and DDR routes. TI strongly recommends that simulation be performed on the higher speed source-synchronous interfaces, such as RGMII, OSPI, and QSPI. Routing for these interfaces should be completed at this time.

Special care is needed for the 3.3 μF output capacitor connected to the CAP_VDDSHV_MMC1 pin on the SoC. This capacitor should be placed as close to the pin as possible and a low inductance path should be present between the CAP_VDDSHV_MMC1 output and the VDDSHV5 voltage pins for the MMC1 IO voltage. This allows the internal LDO to generate either the 3.3 V or 1.8 V needed for an SD Card. The layout used on the AM64 GP EVM is shown in Figure 7-1.

Figure 7-1 AM64 GP EVM Output Capacitor Placement for CAP_VDDSHV_MMC1

This placement can be improved if the capacitor can be placed directly under the SoC. An alternate layout is shown in Figure 7-2.

Figure 7-2 Alternate AM64 GP EVM Output Capacitor Placement for CAP_VDDSHV_MMC1