SPRUIY9B May   2021  – October 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Key Features
  5. 2EVM Revisions and Assembly Variants
  6. 3Important Usage Notes
  7. 4System Description
    1. 4.1 Key Features
    2. 4.2 Functional Block Diagram
    3. 4.3 Power-On/Off Procedures
      1. 4.3.1 Power-On Procedure
      2. 4.3.2 Power-Off Procedure
    4. 4.4 Peripheral and Major Component Description
      1. 4.4.1  Clocking
        1. 4.4.1.1 Ethernet PHY Clock
        2. 4.4.1.2 AM64x SoC Clock
      2. 4.4.2  Reset
      3. 4.4.3  Power
        1. 4.4.3.1 Power Input
        2. 4.4.3.2 USB Type-C Interface for Power Input
        3. 4.4.3.3 Power Fault Indication
        4. 4.4.3.4 Power Supply
        5. 4.4.3.5 Power Sequencing
        6. 4.4.3.6 Power Supply
      4. 4.4.4  Configuration
        1. 4.4.4.1 Boot Modes
      5. 4.4.5  JTAG
      6. 4.4.6  Test Automation
      7. 4.4.7  UART Interface
      8. 4.4.8  Memory Interfaces
        1. 4.4.8.1 LPDDR4 Interface
        2. 4.4.8.2 MMC Interface
          1. 4.4.8.2.1 Micro SD Interface
          2. 4.4.8.2.2 WiLink Interface
          3. 4.4.8.2.3 OSPI Interface
          4. 4.4.8.2.4 Board ID EEPROM Interface
      9. 4.4.9  Ethernet Interface
        1. 4.4.9.1 DP83867 PHY Default Configuration
        2. 4.4.9.2 DP83867 – Power, Clock, Reset, Interrupt and LEDs
        3. 4.4.9.3 Industrial Application LEDs
      10. 4.4.10 USB 3.0 Interface
      11. 4.4.11 PRU Connector
      12. 4.4.12 User Expansion Connector
      13. 4.4.13 MCU Connector
      14. 4.4.14 Interrupt
      15. 4.4.15 I2C Interface
      16. 4.4.16 IO Expander (GPIOs)
  8. 5Known Issues
    1. 5.1 Issue 1: LP8733x Max output Capacitance Spec Exceeded on LDO0 and LDO1
    2. 5.2 Issue 2: LP8733x Output Voltage of 0.9V Exceeds AM64x VDDR_CORE max Voltage Spec of 0.895 V
    3. 5.3 Issue 3 - SDIO Devices on MMC0 Require Careful Trace Lengths to Meet Interface Timing Requirements
    4. 5.4 Issue 4 - LPDDR4 Data Rate Limitation in Stressful Conditions
    5. 5.5 Issue 5 - Junk Character
    6. 5.6 Issue 6 - Test Power Down Signal Floating
    7. 5.7 Issue 7 - uSD Boot Not Working
  9. 6Regulatory Compliance
  10. 7Revision History

4.4.9 Ethernet Interface

SKEVM offers two Ethernet Ports of 1Gigabit Speed for external Communication. Two channels of RGMII Gigabit Ethernet CPSW Ports from AM64xx SoC are connected to two separate Gigabit Ethernet PHY Transceivers DP83867, which is finally terminated on two RJ45 connectors with integrated magnetics.

The 48pin version of the PHY DP83867 is configured to advertise 1-Gb operation with the internal delay set to accommodate the internal delay inside the AM64x. The RGMII1 signals shared with PRG1 are used for the RX path to allow the PRG0 to be connected to the PRU header on the board. CPSW_RGMII1 and CPSW_RGMII2 Ports of PRG1 share a common MDIO Bus to communicate with the external PHY Transceiver.

Two port RJ45 Connector (LPJG16314A4NL) used on the board for Ethernet 10/100/1G Connectivity. RJ45 Connectors have integrated magnetics and LEDs for indicating 1000BASE-T link as well as receive or transmit activity.