SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
Table 3-177 lists the memory-mapped registers for the CLK_CFG_REGS registers. All register offset addresses not listed in Table 3-177 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CLKSEM | Clock Control Semaphore Register | EALLOW | Go |
2h | CLKCFGLOCK1 | Lock bit for CLKCFG registers | EALLOW | Go |
8h | CLKSRCCTL1 | Clock Source Control register-1 | EALLOW | Go |
Ah | CLKSRCCTL2 | Clock Source Control register-2 | EALLOW | Go |
Ch | CLKSRCCTL3 | Clock Source Control register-3 | EALLOW | Go |
Eh | SYSPLLCTL1 | SYSPLL Control register-1 | EALLOW | Go |
14h | SYSPLLMULT | SYSPLL Multiplier register | EALLOW | Go |
16h | SYSPLLSTS | SYSPLL Status register | Go | |
18h | AUXPLLCTL1 | AUXPLL Control register-1 | EALLOW | Go |
1Eh | AUXPLLMULT | AUXPLL Multiplier register | EALLOW | Go |
20h | AUXPLLSTS | AUXPLL Status register | Go | |
22h | SYSCLKDIVSEL | System Clock Divider Select register | EALLOW | Go |
24h | AUXCLKDIVSEL | Auxillary Clock Divider Select register | EALLOW | Go |
26h | PERCLKDIVSEL | Peripheral Clock Divider Select register | EALLOW | Go |
28h | XCLKOUTDIVSEL | XCLKOUT Divider Select register | EALLOW | Go |
2Ah | CLBCLKCTL | CLB Clocking Control Register | EALLOW | Go |
2Ch | LOSPCP | Low Speed Clock Source Prescalar | EALLOW | Go |
2Eh | MCDCR | Missing Clock Detect Control Register | EALLOW | Go |
30h | X1CNT | 10-bit Counter on X1 Clock | Go | |
32h | XTALCR | XTAL Control Register | EALLOW | Go |
3Ah | XTALCR2 | XTAL Control Register for pad init | EALLOW | Go |
3Ch | CLKFAILCFG | Clock Fail cause Configuration | EALLOW | Go |
40h | ETHERCATCLKCTL | EtherCAT Clock Control | EALLOW | Go |
42h | SYNCBUSY | Pulse Transfer Sync Busy Status register | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-178 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CLKSEM is shown in Figure 3-165 and described in Table 3-179.
Return to the Summary Table.
Clock Control Semaphore Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||||||||||
R-0/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEM | ||||||||||||||
R-0-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | Writing the value 0xa5a5 will allow the writing of the SEM bits, else writes are ignored. Reads will return 0. Note: [1] Due to this KEY, only 32-bit writes will succeed (provided the KEY matches). 16-bit writes to the upper or lower half of this register will be ignored Reset type: N/A |
15-2 | RESERVED | R-0 | 0h | Reserved |
1-0 | SEM | R/W | 0h | This register provides a mechanism to acquire all the CLKCFG registers (except this register) by CPU1 or CPU2. A CPU can perform read/writes to any of the CLKCFG registers (except this register) only if it owns the semaphore. Otherwise, writes are ignored and reads will return 0x0. Semaphore State Transitions: A value of 00, 10, 11 gives ownership to CPU1 A value of 01 gives ownership to CPU2. The following are the only state transitions allowed on these bits. 00,11 <-> 01 (allowed by CPU2) 00,11 <-> 10 (allowed by CPU1) If a CPU doesn't own the CLK_CFG_REGS set of registers (as defined by the state of this semaphore), reads from that CPU to all those registers return 0x0 and writes are ignore. Note that this is not true of CLKSEM register. The CLKSEM register's reads and writes are always allowed from both CPU1 and CPU2. Reset type: CPU1.SYSRSn |
CLKCFGLOCK1 is shown in Figure 3-166 and described in Table 3-180.
Return to the Summary Table.
Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ETHERCATCLKCTL | EXTRFLTDET | XTALCR | ||||
R-0-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOSPCP | CLBCLKCTL | PERCLKDIVSEL | AUXCLKDIVSEL | SYSCLKDIVSEL | AUXPLLMULT | RESERVED | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUXPLLCTL1 | SYSPLLMULT | RESERVED | RESERVED | SYSPLLCTL1 | CLKSRCCTL3 | CLKSRCCTL2 | CLKSRCCTL1 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R-0 | 0h | Reserved |
18 | ETHERCATCLKCTL | R/WSonce | 0h | Lock bit for ETHERCATCLKCTL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
17 | EXTRFLTDET | R/WSonce | 0h | Lock bit for EXTRFLTDET register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
16 | XTALCR | R/WSonce | 0h | Common Lock bit for XTALCR & XTAL CR2 register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
15 | LOSPCP | R/WSonce | 0h | Lock bit for LOSPCP register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
14 | CLBCLKCTL | R/WSonce | 0h | Lock bit for CLBCLKCTL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
13 | PERCLKDIVSEL | R/WSonce | 0h | Lock bit for PERCLKDIVSEL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
12 | AUXCLKDIVSEL | R/WSonce | 0h | Lock bit for AUXCLKDIVSEL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
11 | SYSCLKDIVSEL | R/WSonce | 0h | Lock bit for SYSCLKDIVSEL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
10 | AUXPLLMULT | R/WSonce | 0h | Lock bit for AUXPLLMULT register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
9 | RESERVED | R/WSonce | 0h | Reserved |
8 | RESERVED | R/WSonce | 0h | Reserved |
7 | AUXPLLCTL1 | R/WSonce | 0h | Lock bit for AUXPLLCTL1 register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
6 | SYSPLLMULT | R/WSonce | 0h | Lock bit for SYSPLLMULT register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
5 | RESERVED | R/WSonce | 0h | Reserved |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | SYSPLLCTL1 | R/WSonce | 0h | Lock bit for SYSPLLCTL1 register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
2 | CLKSRCCTL3 | R/WSonce | 0h | Lock bit for CLKSRCCTL3 register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
1 | CLKSRCCTL2 | R/WSonce | 0h | Lock bit for CLKSRCCTL2 register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
0 | CLKSRCCTL1 | R/WSonce | 0h | Lock bit for CLKSRCCTL1 register: 0: Respective register is not locked 1: Respective register is locked. Reset type: CPU1.SYSRSn |
CLKSRCCTL1 is shown in Figure 3-167 and described in Table 3-181.
Return to the Summary Table.
Clock Source Control register-1
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | WDHALTI | RESERVED | RESERVED | RESERVED | OSCCLKSRCSEL | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R-0 | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | WDHALTI | R/W | 0h | Watchdog HALT Mode Ignore Bit: This bit determines if WD is functional in the HALT mode or not. 0 = WD is not functional in the HALT mode. Clock to WD is gated when system enters HALT mode. 1 = WD is functional in the HALT mode. Clock to WD is not gated Reset type: XRSn |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R-0 | 0h | Reserved |
1-0 | OSCCLKSRCSEL | R/W | 0h | Oscillator Clock Source Select Bit: This bit selects the source for OSCCLK. 00 = INTOSC2 (default on reset) 01 = External Oscillator (XTAL) 10 = INTOSC1 11 = reserved (default to INTOSC1) At power-up or after an XRSn, INTOSC2 is selected by default. Whenever the user changes the clock source using these bits, the SYSPLLMULT[13:0] register will be forced to zero and the PLL will be bypassed and powered down. This prevents potential PLL overshoot. The user will then have to write to the SYSPLLMULT register to configure the appropriate multiplier. The user must wait 10 OSCCLK cycles before writing to SYSPLLMULT or disabling the previous clock source to allow the change to complete.. Notes: [1] INTOSC1 is recommended to be used only after missing clock detection. If user wants to re-lock the PLL with INTOSC1 (the back-up clock source) after missing clock is detected, he can do a MCLKCLR and lock the PLL. Reset type: XRSn |
CLKSRCCTL2 is shown in Figure 3-168 and described in Table 3-182.
Return to the Summary Table.
Clock Source Control register-2
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MCANBBCLKSEL | MCANABCLKSEL | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CANABCLKSEL | AUXOSCCLKSRCSEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | MCANBBCLKSEL | R/W | 0h | MCAN Bit Clock Source Select Bit: 00 = PERx.SYSCLK 01 = AUXPLLRAWCLK 10 = AUXCLKIN 11 = PLLRAWCLK Missing clock detect circuit doesnt have any impact on these bits. Reset type: XRSn |
11-10 | MCANABCLKSEL | R/W | 0h | MCAN Bit Clock Source Select Bit: 00 = PERx.SYSCLK 01 = AUXPLLRAWCLK 10 = AUXCLKIN 11 = PLLRAWCLK Missing clock detect circuit doesnt have any impact on these bits. Reset type: XRSn |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | CANABCLKSEL | R/W | 0h | CANA Bit-Clock Source Select Bit: 00 = PERx.SYSCLK (default on reset) 01 = External Oscillator (XTAL) 10 = Reserved 11 = Reserved Missing clock detect circuit doesnt have any impact on these bits. Reset type: XRSn |
1-0 | AUXOSCCLKSRCSEL | R/W | 0h | Oscillator Clock Source Select Bit: This bit selects the source for AUXOSCCLK: 00 = INTOSC2 (default on reset) 01 = External Oscillator (XTAL) 10 = AUXCLKIN (from GPIO) 11 = Reserved Whenever the user changes the clock source using these bits, the AUXPLLMULT register will be forced to zero and the PLL will be bypassed and powered down. This prevents potential PLL overshoot. The user will then have to write to the AUXPLLMULT register to configure the appropriate multiplier. The user must wait 10 OSCCLK cycles before writing to AUXPLLMULT or disabling the previous clock source to allow the change to complete. The missing clock detection circuit does not affect these bits. Reset type: XRSn |
CLKSRCCTL3 is shown in Figure 3-169 and described in Table 3-183.
Return to the Summary Table.
Clock Source Control register-3
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XCLKOUTSEL | ||||||||||||||
R-0-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3-0 | XCLKOUTSEL | R/W | 0h | XCLKOUT Source Select Bit: This bit selects the source for XCLKOUT: 0000 = PLLSYSCLK (default on reset) 0001 = PLLCLK (After the Bypass Mux) 0010 = CPU1.SYSCLK 0011 = CPU2.SYSCLK 0100 = AUXPLLCLK (After the Bypass Mux) 0101 = INTOSC1 0110 = INTOSC2 0111 = XTAL OSC o/p clock 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = Reserved 1100 = SYSPLLRAWCLK 1101 = AUXPLLRAWCLK Rest = Reserved Reset type: CPU1.SYSRSn |
SYSPLLCTL1 is shown in Figure 3-170 and described in Table 3-184.
Return to the Summary Table.
SYSPLL Control register-1
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | PLLCLKEN | PLLEN | |
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R-0 | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | PLLCLKEN | R/W | 0h | SYSPLL bypassed or included in the PLLSYSCLK path: This bit decides if the SYSPLL is bypassed when PLLSYSCLK is generated 1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need to make sure that the PLL is locked before enabling this clock to the system. 0 = SYSPLL is bypassed. Clock to system is direct feed from OSCCLK Reset type: XRSn |
0 | PLLEN | R/W | 0h | SYSPLL enabled or disabled: This bit decides if the SYSPLL is enabled or not 1 = SYSPLL is enabled 0 = SYSPLL is powered off. Clock to system is direct feed from OSCCLK Reset type: XRSn |
SYSPLLMULT is shown in Figure 3-171 and described in Table 3-185.
Return to the Summary Table.
SYSPLL Multiplier register
NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | REFDIV | ||||||
R-0-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ODIV | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0-0h | R/W-0h | R-0-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMULT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R-0 | 0h | Reserved |
28-24 | REFDIV | R/W | 0h | SYSPLL Reference Clock Divider PLL Reference Divider = REFDIV + 1 Reset type: XRSn |
23-21 | RESERVED | R-0 | 0h | Reserved |
20-16 | ODIV | R/W | 0h | SYSPLL Output Clock Divider PLL Output Divider = ODIV + 1 ODIV should be set to 1 or greater to ensure the PLL output meets duty cycle requirements. Reset type: XRSn |
15-14 | RESERVED | R-0 | 0h | Reserved |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | RESERVED | R-0 | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-0 | IMULT | R/W | 0h | SYSPLL Integer Multiplier: For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1 0000001 Integer Multiplier = 1 0000010 Integer Multiplier = 2 0000011 Integer Multiplier = 3 ....... 1111111 Integer Multipler = 127 Note for APLL Multiplier values from 0-3 are invalid, internally those will be treated to 4. Reset type: XRSn |
SYSPLLSTS is shown in Figure 3-172 and described in Table 3-186.
Return to the Summary Table.
SYSPLL Status register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | REF_LOSTS | RESERVED | SLIPS_NOTSUPPORTED | LOCKS | |
R-0-0h | R-1h | R-1h | W1C-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R-0 | 0h | Reserved |
5 | RESERVED | R | 1h | Reserved |
4 | RESERVED | R | 1h | Reserved |
3 | REF_LOSTS | W1C | 0h | SYSPLL 'Reference Lost' Status Bit: This bit indicates whether the SYSPLL is out of lock range 0 = 'Reference Lost' event has not occurred. 1 = 'Reference Lost' event has occurred. Reset type: XRSn |
2 | RESERVED | R | 0h | Reserved |
1 | SLIPS_NOTSUPPORTED | R | 0h | RESERVED: This bit is reserved and the value read should be ignored. TI recommends using DCC to evaluate SYSPLL Slip status. Refer to InitSysPll() or SysCtl_setClock() functions inside the latest example software from C2000Ware for checking SYSPLL Slip status using DCC. Reset type: XRSn |
0 | LOCKS | R | 0h | SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is locked or not 0 = SYSPLL is not yet locked 1 = SYSPLL is locked Reset type: XRSn |
AUXPLLCTL1 is shown in Figure 3-173 and described in Table 3-187.
Return to the Summary Table.
AUXPLL Control register-1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | PLLCLKEN | PLLEN | |
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R-0 | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | PLLCLKEN | R/W | 0h | AUXPLL bypassed or included in the AUXPLLCLK path: This bit decides if the AUXPLL is bypassed when AUXPLLCLK is generated 1 = AUXPLLCLK is fed from the AUXPLL clock output. Users need to make sure that the PLL is locked before enabling this clock to the AUXPLLCLK connected modules. 0 = AUXPLL is bypassed. Clock to modules connected to AUXPLLCLK is direct feed from AUXOSCCLK Reset type: XRSn |
0 | PLLEN | R/W | 0h | AUXPLL enabled or disabled: This bit decides if the AUXPLL is enabled or not 1 = AUXPLL is enabled 0 = AUXPLL is powered off. Clock to system is direct feed from AUXOSCCLK Reset type: XRSn |
AUXPLLMULT is shown in Figure 3-174 and described in Table 3-188.
Return to the Summary Table.
AUXPLL Multiplier register
NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | REFDIV | ||||||
R-0-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ODIV | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0-0h | R/W-0h | R-0-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMULT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R-0 | 0h | Reserved |
28-24 | REFDIV | R/W | 0h | AUXPLL Reference Clock Divider PLL Reference Divider = REFDIV + 1 Reset type: XRSn |
23-21 | RESERVED | R-0 | 0h | Reserved |
20-16 | ODIV | R/W | 0h | AUXPLL Output Clock Divider
PLL Output Divider = ODIV + 1 ODIV should be set to 1 or greater to ensure the PLL output meets duty cycle requirements. Reset type: XRSn |
15-14 | RESERVED | R-0 | 0h | Reserved |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | RESERVED | R-0 | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-0 | IMULT | R/W | 0h | AUXPLL Integer Multiplier: For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1 0000001 Integer Multiplier = 1 0000010 Integer Multiplier = 2 0000011 Integer Multiplier = 3 ....... 1111111 Integer Multipler = 127 Note for APLL Multiplier values from 0-3 are invalid, internally those will be treated to 4. Reset type: XRSn |
AUXPLLSTS is shown in Figure 3-175 and described in Table 3-189.
Return to the Summary Table.
AUXPLL Status register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | REF_LOSTS | RESERVED | SLIPS_NOTSUPPORTED | LOCKS | |
R-0-0h | R-1h | R-1h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R-0 | 0h | Reserved |
5 | RESERVED | R | 1h | Reserved |
4 | RESERVED | R | 1h | Reserved |
3 | REF_LOSTS | R | 0h | AUXPLL 'Reference Lost' Status Bit: This bit indicates whether the AUXPLL is out of lock range 0 = 'Reference Lost' event has not occurred. 1 = 'Reference Lost' event has occurred. Reset type: XRSn |
2 | RESERVED | R | 0h | Reserved |
1 | SLIPS_NOTSUPPORTED | R | 0h | RESERVED: This bit is reserved and the value read should be ignored. TI recommends using DCC to evaluate AUXPLL Slip status. Refer to InitAuxPll() or SysCtl_setAuxClock() functions inside the latest example software from C2000Ware for checking AUXPLL Slip status using DCC. Reset type: XRSn |
0 | LOCKS | R | 0h | AUXPLL Lock Status Bit: This bit indicates whether the AUXPLL is locked or not 0 = AUXPLL is not yet locked 1 = AUXPLL is locked Reset type: XRSn |
SYSCLKDIVSEL is shown in Figure 3-176 and described in Table 3-190.
Return to the Summary Table.
System Clock Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PLLSYSCLKDIV_LSB | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLLSYSCLKDIV | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R-0 | 0h | Reserved |
8 | PLLSYSCLKDIV_LSB | R/W | 0h | This bit is LSB of the Divider that when set allows the ODD divisions such that the divider value is {PLLSYSCLKDIV,PLLSYSCLKDIV_LSB}. E.g. if PLLSYSCLKDIV=0x1, and PLLSYSCLKDIV_LSB=0 then divider of 2 is used else in case PLLSYSCLKDIV_LSB=1 then divider value is 3. Reset type: XRSn |
7-6 | RESERVED | R-0 | 0h | Reserved |
5-0 | PLLSYSCLKDIV | R/W | 0h | PLLSYSCLK Divide Select: This bit selects the divider setting for the PLLSYSCLK. 000000 = /1 000001 = /2 000010 = /4 (Default) 000011 = /6 000100 = /8 ...... 111111 = /126 Reset type: XRSn |
AUXCLKDIVSEL is shown in Figure 3-177 and described in Table 3-191.
Return to the Summary Table.
Auxillary Clock Divider Select register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MCANBCLKDIV | ||||||||||||||
R-0-0h | R/W-13h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCANBCLKDIV | MCANACLKDIV | RESERVED | AUXPLLDIV | ||||||||||||
R/W-13h | R/W-13h | R-0-0h | R/W-1h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17-13 | MCANBCLKDIV | R/W | 13h | 00000 = /1 00001 = /2 ... 10010 = /19 10011 = /20 101xx = Rsvd 11xxx = Rsvd Reset type: XRSn |
12-8 | MCANACLKDIV | R/W | 13h | 00000 = /1 00001 = /2 ... 10010 = /19 10011 = /20 101xx = Rsvd 11xxx = Rsvd Reset type: XRSn |
7-3 | RESERVED | R-0 | 0h | Reserved |
2-0 | AUXPLLDIV | R/W | 1h | AUXPLLCLK Divide Select: This bit selects the divider setting for the AUXPLLCK. 000 = /1 001 = /2 (default on reset) 010 = /4 011 = /8 100 = /3 101 = /5 110 = /6 111 = /7 Reset type: XRSn |
PERCLKDIVSEL is shown in Figure 3-178 and described in Table 3-192.
Return to the Summary Table.
Peripheral Clock Divider Select register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LINBCLKDIV | RESERVED | LINACLKDIV | ||||
R-0-0h | R/W-1h | R-0-0h | R/W-1h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | EMIF1CLKDIV | RESERVED | EPWMCLKDIV | ||
R-0-0h | R/W-1h | R-0-0h | R/W-1h | R/W-0h | R/W-1h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R-0 | 0h | Reserved |
12-11 | LINBCLKDIV | R/W | 1h | LINB Clock Divide Select: This bit selects whether the LINB module runs with a /1, /2, or /4 clock. 00: /1 of SYSCLK is selected 01: /2 of SYSCLK is selected 10: /4 of SYSCLK is selected 11: Reserved Reset type: CPU1.SYSRSn |
10 | RESERVED | R-0 | 0h | Reserved |
9-8 | LINACLKDIV | R/W | 1h | LINA Clock Divide Select: This bit selects whether the LINA module runs with a /1, /2, or /4 clock. 00: /1 of SYSCLK is selected 01: /2 of SYSCLK is selected 10: /4 of SYSCLK is selected 11: Reserved Reset type: CPU1.SYSRSn |
7 | RESERVED | R-0 | 0h | Reserved |
6 | RESERVED | R/W | 1h | Reserved |
5 | RESERVED | R-0 | 0h | Reserved |
4 | EMIF1CLKDIV | R/W | 1h | EMIF1 Clock Divide Select: This bit selects whether the EMIF1 module run with a /1 or /2 clock. For single core device 0: /1 of SYSCLK is selected 1: /2 of SYSCLK is selected For Dual core device 0: /1 of PLLSYSCLK is selected 1: /2 of PLLSYSCLK is selected Reset type: CPU1.SYSRSn |
3-2 | RESERVED | R/W | 0h | Reserved |
1-0 | EPWMCLKDIV | R/W | 1h | EPWM Clock Divide Select: This bit selects whether the EPWM modules run with a /1 or /2 clock. This divider sits in front of the PLLSYSCLK x0 = /1 of PLLSYSCLK x1 = /2 of PLLSYSLCK Note: Refer to the EPWM User Guide for maximum EPWM Frequency Reset type: CPU1.SYSRSn |
XCLKOUTDIVSEL is shown in Figure 3-179 and described in Table 3-193.
Return to the Summary Table.
XCLKOUT Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XCLKOUTDIV | ||||||
R-0-0h | R/W-3h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1-0 | XCLKOUTDIV | R/W | 3h | XCLKOUT Divide Select: This bit selects the divider setting for the XCLKOUT. 00 = /1 01 = /2 10 = /4 11 = /8 (default on reset) Reset type: CPU1.SYSRSn |
CLBCLKCTL is shown in Figure 3-180 and described in Table 3-194.
Return to the Summary Table.
CLB Clocking Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | CLKMODECLB6 | CLKMODECLB5 | CLKMODECLB4 | CLKMODECLB3 | CLKMODECLB2 | CLKMODECLB1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0-0h | R/W-0h | R-0-0h | R/W-7h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R-0 | 0h | Reserved |
23 | RESERVED | R/W | 0h | Reserved |
22 | RESERVED | R/W | 0h | Reserved |
21 | CLKMODECLB6 | R/W | 0h | 0 : CLB6 is synchronous to SYSCLK 1 : CLB6 runs of asynchronous clock Reset type: SYSRSn |
20 | CLKMODECLB5 | R/W | 0h | 0 : CLB5 is synchronous to SYSCLK 1 : CLB5 runs of asynchronous clock Reset type: SYSRSn |
19 | CLKMODECLB4 | R/W | 0h | 0 : CLB4 is synchronous to SYSCLK 1 : CLB4 runs of asynchronous clock Reset type: SYSRSn |
18 | CLKMODECLB3 | R/W | 0h | 0 : CLB3 is synchronous to SYSCLK 1 : CLB3 runs of asynchronous clock Reset type: SYSRSn |
17 | CLKMODECLB2 | R/W | 0h | 0 : CLB2 is synchronous to SYSCLK 1 : CLB2 runs of asynchronous clock Reset type: SYSRSn |
16 | CLKMODECLB1 | R/W | 0h | 0 : CLB1 is synchronous to SYSCLK 1 : CLB1 runs of asynchronous clock Reset type: SYSRSn |
15-5 | RESERVED | R-0 | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R-0 | 0h | Reserved |
2-0 | RESERVED | R/W | 7h | Reserved |
LOSPCP is shown in Figure 3-181 and described in Table 3-195.
Return to the Summary Table.
Low Speed Clock Source Prescalar
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LSPCLKDIV | ||||||||||||||
R-0-0h | R/W-2h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R-0 | 0h | Reserved |
2-0 | LSPCLKDIV | R/W | 2h | These bits configure the low-speed peripheral clock (LSPCLK) rate 000,LSPCLK = / 1 001,LSPCLK = / 2 010,LSPCLK = / 4 (default on reset) 011,LSPCLK = / 6 100,LSPCLK = / 8 101,LSPCLK = / 10 110,LSPCLK = / 12 111,LSPCLK = / 14 Note: [1] This clock is used as strobe for the SCI and SPI modules. Reset type: CPU1.SYSRSn |
MCDCR is shown in Figure 3-182 and described in Table 3-196.
Return to the Summary Table.
Missing Clock Detect Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | EXTR_FAULT_MCD_EN | EXTR_FAULTSCLR | EXTR_FAULTS | AUXREF_LOST_MCD_EN | AUXREF_LOSTSCLR |
R-0-0h | R/W-1h | R/W-1h | R/W-0h | R-0/W1S-0h | R-0h | R/W-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUXREF_LOSTS | SYSREF_LOST_MCD_EN | SYSREF_LOSTSCLR | SYSREF_LOSTS | OSCOFF | MCLKOFF | MCLKCLR | MCLKSTS |
R-0h | R/W-0h | R-0/W1S-0h | R-0h | R/W-0h | R/W-0h | R-0/W1S-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R-0 | 0h | Reserved |
14 | RESERVED | R/W | 1h | Reserved |
13 | RESERVED | R/W | 1h | Reserved |
12 | EXTR_FAULT_MCD_EN | R/W | 0h | Control to add 'EXTR FAULTt' as cause for MCD 0 = 'EXTR FAULT' does not affect MCD. 1 = Upon 'EXTR FAULT' MCD is asserted. Reset type: XRSn |
11 | EXTR_FAULTSCLR | R-0/W1S | 0h | Clears the EXTR_FAULTS from MCDCR which is root for MCD trigger. 0 = No effect on present state of the EXTR_FAULTS 1 = Clears the EXTR_FAULTS bit to '0'. Bit clears itself after clear pulse to EXTR_FAULTS. Read always gives '0'. Reset type: XRSn |
10 | EXTR_FAULTS | R | 0h | External Resistor fault status Bit: This bit indicates whether there is a critical fault in the external resistor connected to the device 0 = 'EXTR fault' event has not occurred. 1 = 'EXTR fault' event has occurred. Reset type: XRSn |
9 | AUXREF_LOST_MCD_EN | R/W | 0h | Control to add 'PLL reference clock lost' as cause for MCD 0 = 'PLL reference clock Lost' does not affect MCD. 1 = Upon 'PLL reference clock Lost' MCD is asserted. Reset type: XRSn |
8 | AUXREF_LOSTSCLR | R-0/W1S | 0h | Clears the AUXREF_LOSTS from PLLSTS which is root for MCD trigger. 0 = No effect on present state of the AUXREF_LOSTS 1 = Clears the AUXREF_LOSTS bit to '0'. Bit clears itself after clear pulse to AUXREF_LOSTS. Read always gives '0'. Reset type: XRSn |
7 | AUXREF_LOSTS | R | 0h | AUXPLL 'Reference Lost' Status Bit: This bit indicates whether the AUXPLL is out of lock range 0 = 'Reference Lost' event has not occurred. 1 = 'Reference Lost' event has occurred. Reset type: XRSn |
6 | SYSREF_LOST_MCD_EN | R/W | 0h | Control to add 'PLL reference clock lost' as cause for MCD 0 = 'PLL reference clock Lost' does not affect MCD. 1 = Upon 'PLL reference clock Lost' MCD is asserted. Reset type: XRSn |
5 | SYSREF_LOSTSCLR | R-0/W1S | 0h | Clears the REF_LOST_STS from PLLSTS which is root for MCD trigger. 0 = No effect on present state of the REF_LOST_STS 1 = Clears the REF_LOST_STS bit to '0'. Bit clears itself after clear pulse to REF_LOST_STS. Read always gives '0'. Reset type: XRSn |
4 | SYSREF_LOSTS | R | 0h | SYSPLL 'Reference Lost' Status Bit: This bit indicates whether the SYSPLL is out of lock range 0 = 'Reference Lost' event has not occurred. 1 = 'Reference Lost' event has occurred. Reset type: XRSn |
3 | OSCOFF | R/W | 0h | Oscillator Clock Disconnect from MCD Bit: 0 = OSCCLK Connected to OSCCLK Counter in MCD module 1 = OSCCLK Disconnected to OSCCLK Counter in MCD module Reset type: XRSn |
2 | MCLKOFF | R/W | 0h | Missing Clock Detect Off Bit: 0 = Missing Clock Detect Circuit Enabled 1 = Missing Clock Detect Circuit Disabled Reset type: XRSn |
1 | MCLKCLR | R-0/W1S | 0h | Missing Clock Clear Bit: Write 1' to this bit to clear MCLKSTS bit and reset the missing clock detect circuit.' Reset type: XRSn |
0 | MCLKSTS | R | 0h | Missing Clock Status Bit: 0 = OSCCLK Is OK 1 = OSCCLK Detected Missing, CLOCKFAILn Generated Reset type: XRSn |
X1CNT is shown in Figure 3-183 and described in Table 3-197.
Return to the Summary Table.
10-bit Counter on X1 Clock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CLR | ||||||||||||||
R-0-0h | R-0/W1C-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | X1CNT | ||||||||||||||
R-0-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R-0 | 0h | Reserved |
16 | CLR | R-0/W1C | 0h | X1 Counter clear: A write of '1' to this bit field clears the X1CNT and makes it count from 0x0 again (provided X1 clock is ticking). Writes of '0' are ignore to this bit field Reset type: XRSn |
15-11 | RESERVED | R-0 | 0h | Reserved |
10-0 | X1CNT | R | 0h | X1 Counter: - This counter increments on every X1 CLOCKs positive-edge. - Once it reaches the values of 0x7ff, it freezes - Before switching from INTOSC2 to X1, application must check this counter and make sure that it has saturated. This will ensure that the Crystal connected to X1/X2 is oscillating. Reset type: XRSn |
XTALCR is shown in Figure 3-184 and described in Table 3-198.
Return to the Summary Table.
XTAL Control Register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | SE | OSCOFF | ||||
R-0-0h | R/W-1h | R/W-0h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R-0 | 0h | Reserved |
2 | RESERVED | R/W | 1h | Reserved |
1 | SE | R/W | 0h | Configures XTAL oscillator in single-ended or Crystal mode when XTAL oscillator is powered up(i.e. OSCOFF = 0) 0 XTAL oscillator in Crystal mode 1 XTAL oscilator in single-ended mode (through X1) Reset type: XRSn |
0 | OSCOFF | R/W | 1h | This bit if '1', powers-down the XTAL oscillator macro and hence doesn't let X2 to be driven by the XTAL oscillator. If a crystal is connected to X1/X2, user needs to first clear this bit, wait for the oscillator to power up (using X1CNT) and then only switch the clock source to X1/X2 Reset type: XRSn |
XTALCR2 is shown in Figure 3-185 and described in Table 3-199.
Return to the Summary Table.
XTAL Control Register for pad init
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FEN | XOF | XIF | ||||||||||||
R-0-0h | R/W-0h | R/W-1h | R/W-1h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | Reserved |
15-3 | RESERVED | R-0 | 0h | Reserved |
2 | FEN | R/W | 0h | Configures XTAL oscillator pad initilisation. 0 : XOSC pads are not driven through GPIO connection. 1 : XOSC pads are driven through connected GPIO as per XIF & XOF values. This register has effect only when XOSC is OFF (no SE , no XTAL mode). If this register is set during XOSC off state (XOSCOFF=1 & SE=0) then upon change of these controls this bit gets reset and rearmed. Reset type: XRSn |
1 | XOF | R/W | 1h | Polarity selection to initialise XO /X2 pad of the XOSC before start-up This value shall be deposited on the pad before XOSC started (XOSCOFF=1) If FEN=0 or XOSC is in XTAL or SE mode then this value will not be applied to the pad. Reset type: XRSn |
0 | XIF | R/W | 1h | Polarity selection to initialise XI /X1 pad of the XOSC before start-up This value shall be deposited on the pad before XOSC started (XOSCOFF=1) If FEN=0 or XOSC is in XTAL or SE mode then this value will not be applied to the pad. Reset type: XRSn |
CLKFAILCFG is shown in Figure 3-186 and described in Table 3-200.
Return to the Summary Table.
Clock Fail cause Configuration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DCC2_ERROR_EN | DCC1_ERROR_EN | DCC0_ERROR_EN | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R-0 | 0h | Reserved |
2 | DCC2_ERROR_EN | R/W | 0h | This field enables DCC2 Error to cause the clock-fail NMI to get asserted. 0 : DCC2 Error does not affect Clock fail NMI 1: Occurrence of DCC2 Error triggers Clock fail NMI assertion and ERROR pin assertion. Reset type: XRSn |
1 | DCC1_ERROR_EN | R/W | 0h | This field enables DCC1 Error to cause the clock-fail NMI to get asserted. 0 : DCC1 Error does not affect Clock fail NMI 1: Occurrence of DCC1 Error triggers Clock fail NMI assertion and ERROR pin assertion. Reset type: XRSn |
0 | DCC0_ERROR_EN | R/W | 0h | This field enables DCC0 Error to cause the clock-fail NMI to get asserted. 0 : DCC0 Error does not affect Clock fail NMI 1: Occurrence of DCC0 Error triggers Clock fail NMI assertion and ERROR pin assertion. Reset type: XRSn |
ETHERCATCLKCTL is shown in Figure 3-187 and described in Table 3-201.
Return to the Summary Table.
EtherCAT Clock Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PHYCLKEN | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECATDIV | DIVSRCSEL | |||||
R-0-0h | R/W-7h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | PHYCLKEN | R/W | 0h | 0 : etherCAT phy clock disabled 1 : etherCAT phy clock enabled Reset type: XRSn |
7-4 | RESERVED | R-0 | 0h | Reserved |
3-1 | ECATDIV | R/W | 7h | 000: /1 001: /2 010: /3 011: /4 100: /5 101: /6 110: /7 111: /8 Reset type: XRSn |
0 | DIVSRCSEL | R/W | 0h | 0: Auxillary PLL is the source for the etherCAT clock divider. 1: System PLL is the source for etherCAT clock divider. Reset type: XRSn |
SYNCBUSY is shown in Figure 3-188 and described in Table 3-202.
Return to the Summary Table.
Pulse Transfer Sync Busy Status register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU2TMR2CTL | CPU1TMR2CTL | CLKSRCCTL3 | CLKSRCCTL2 | CLKSRCCTL1 | XTALCR | XCLKOUTDIVSEL | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SYSPLLMULT | SYSPLLCTL1 | SYSCLKDIVSEL | PERCLKDIVSEL | ETHERCATCLKCTL | CLBCLKCTL | AUXPLLMULT | AUXCLKDIVSEL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BUSY | ||||||
R-0-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU2TMR2CTL | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
30 | CPU1TMR2CTL | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
29 | CLKSRCCTL3 | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
28 | CLKSRCCTL2 | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
27 | CLKSRCCTL1 | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
26 | XTALCR | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
25 | XCLKOUTDIVSEL | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
24 | RESERVED | R | 0h | Reserved |
23 | SYSPLLMULT | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
22 | SYSPLLCTL1 | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
21 | SYSCLKDIVSEL | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
20 | PERCLKDIVSEL | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
19 | ETHERCATCLKCTL | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
18 | CLBCLKCTL | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
17 | AUXPLLMULT | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
16 | AUXCLKDIVSEL | R | 0h | This status bit indicates write to the register is in progress 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |
15-1 | RESERVED | R-0 | 0h | Reserved |
0 | BUSY | R | 0h | This status bit indicates write to any of the following registers (OR_REDUCE) is in progress or not. AUXCLKDIVSEL, AUXPLLMULT, CLBCLKCTL, ETHERCATCLKCTL, PERCLKDIVSEL, SYSCLKDIVSEL, SYSPLLCTL1, SYSPLLMULT, XCLKOUTDIVSEL, XTALCR, CLKSRCCTL1, CLKSRCCTL2, CLKSRCCTL3, CPU1TMR2CTL, CPU2TMR2CTL 0 : Not BUSY - No synchronization in progress 1 : BUSY - Synchronization is in progress Reset type: SYSRSn |