SPRUIZ1B July   2023  – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit (FPU)
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 VCRC Unit
  5. 3 C28x System Control and Interrupts
    1. 3.1  C28x System Control Introduction
      1. 3.1.1 SYSCTL Related Collateral
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
    3. 3.3  Resets
      1. 3.3.1  Reset Sources
      2. 3.3.2  External Reset (XRS)
      3. 3.3.3  Simulate External Reset (SIMRESET.XRS)
      4. 3.3.4  Power-On Reset (POR)
      5. 3.3.5  Debugger Reset (SYSRS)
      6. 3.3.6  Simulate CPU1 Reset (SIMRESET)
      7. 3.3.7  Watchdog Reset (WDRS)
      8. 3.3.8  NMI Watchdog Reset (NMIWDRS)
      9. 3.3.9  Secure Code Copy Reset (SCCRESET)
      10. 3.3.10 EtherCAT SubDevice Controller (ESC) Module Reset Output
    4. 3.4  Peripheral Interrupts
      1. 3.4.1 Interrupt Concepts
      2. 3.4.2 Interrupt Architecture
        1. 3.4.2.1 Peripheral Stage
        2. 3.4.2.2 PIE Stage
        3. 3.4.2.3 CPU Stage
        4. 3.4.2.4 Dual-CPU Interrupt Handling
      3. 3.4.3 Interrupt Entry Sequence
      4. 3.4.4 Configuring and Using Interrupts
        1. 3.4.4.1 Enabling Interrupts
        2. 3.4.4.2 Handling Interrupts
        3. 3.4.4.3 Disabling Interrupts
        4. 3.4.4.4 Nesting Interrupts
      5. 3.4.5 PIE Channel Mapping
        1. 3.4.5.1 PIE Interrupt Priority
          1. 3.4.5.1.1 Channel Priority
          2. 3.4.5.1.2 Group Priority
      6. 3.4.6 System Error Interrupts
      7. 3.4.7 Vector Tables
    5. 3.5  Exceptions and Non-Maskable Interrupts
      1. 3.5.1 Configuring and Using NMIs
      2. 3.5.2 Emulation Considerations
      3. 3.5.3 NMI Sources
        1. 3.5.3.1 Missing Clock Detection
        2. 3.5.3.2 RAM Uncorrectable Error
        3. 3.5.3.3 Flash Uncorrectable ECC Error
        4. 3.5.3.4 ROM Uncorrectable Error
        5. 3.5.3.5 NMI Vector Fetch Mismatch
        6. 3.5.3.6 CPU2 Watchdog or NMI Watchdog Reset
        7. 3.5.3.7 EtherCAT Reset Out
        8. 3.5.3.8 CRC Fail
        9. 3.5.3.9 ERAD NMI
      4. 3.5.4 Illegal Instruction Trap (ITRAP)
    6. 3.6  Safety Features
      1. 3.6.1 Write Protection on Registers
        1. 3.6.1.1 LOCK Protection on System Configuration Registers
        2. 3.6.1.2 EALLOW Protection
      2. 3.6.2 CPU1 and CPU2 ePIE Vector Address Validity Check
      3. 3.6.3 NMIWDs
      4. 3.6.4 ECC and Parity Enabled RAMs, Shared RAMs Protection
      5. 3.6.5 ECC Enabled Flash Memory
      6. 3.6.6 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1 Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
        4. 3.7.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.7.2 Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
        3. 3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
        4. 3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
      3. 3.7.3 Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)
        6. 3.7.3.6 CAN Bit Clock
        7. 3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4 External Clock Output (XCLKOUT)
      5. 3.7.5 Clock Connectivity
      6. 3.7.6 Using an External Crystal or Resonator
        1. 3.7.6.1 X1/X2 Precondition Circuit
      7. 3.7.7 PLL/AUXPLL
        1. 3.7.7.1 System Clock Setup
        2. 3.7.7.2 USB Auxiliary Clock Setup
        3. 3.7.7.3 SYS PLL/AUX PLL Bypass
      8. 3.7.8 Clock (OSCCLK) Failure Detection
        1. 3.7.8.1 Missing Clock Detection Logic
    8. 3.8  Clock Configuration Semaphore
    9. 3.9  32-Bit CPU Timers 0/1/2
    10. 3.10 Watchdog Timers
      1. 3.10.1 Servicing the Watchdog Timer
      2. 3.10.2 Minimum Window Check
      3. 3.10.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.10.4 Watchdog Operation in Low-Power Modes
      5. 3.10.5 Emulation Considerations
    11. 3.11 Low-Power Modes
      1. 3.11.1 IDLE
      2. 3.11.2 STANDBY
      3. 3.11.3 HALT
    12. 3.12 Memory Controller Module
      1. 3.12.1  Dedicated RAM (Dx RAM)
      2. 3.12.2  Local Shared RAM (LSx RAM)
      3. 3.12.3  Global Shared RAM (GSx RAM)
      4. 3.12.4  CPU Message RAM (CPU MSG RAM)
      5. 3.12.5  CLA Message RAM (CLA MSGRAM)
      6. 3.12.6  CLA-DMA MSG RAM
      7. 3.12.7  Access Arbitration
      8. 3.12.8  Access Protection
        1. 3.12.8.1 CPU Fetch Protection
        2. 3.12.8.2 CPU Write Protection
        3. 3.12.8.3 CPU Read Protection
        4. 3.12.8.4 CLA Fetch Protection
        5. 3.12.8.5 CLA Write Protection
        6. 3.12.8.6 CLA Read Protection
        7. 3.12.8.7 DMA Write Protection
      9. 3.12.9  Memory Error Detection, Correction, and Error Handling
        1. 3.12.9.1 Error Detection and Correction
        2. 3.12.9.2 Error Handling
      10. 3.12.10 Application Test Hooks for Error Detection and Correction
      11. 3.12.11 ROM Test
      12. 3.12.12 RAM Initialization
    13. 3.13 JTAG
      1. 3.13.1 JTAG Noise and TAP_STATUS
    14. 3.14 Live Firmware Update (LFU)
      1. 3.14.1 LFU Background
      2. 3.14.2 LFU Switchover Steps
      3. 3.14.3 Device Features Supporting LFU
        1. 3.14.3.1 Multi-Bank Flash
        2. 3.14.3.2 PIE Vector Table Swap
        3. 3.14.3.3 LS0/LS1 RAM Memory Swap for CPU1
          1. 3.14.3.3.1 Applicability to CLA LFU
        4. 3.14.3.4 D2/D3 RAM Memory Swap for CPU2
        5. 3.14.3.5 Additional Points Pertaining to LS0/LS1 and D2/D3 RAM Memory Swap
      4. 3.14.4 LFU Switchover
      5. 3.14.5 LFU Resources
    15. 3.15 System Control Register Configuration Restrictions
    16. 3.16 MCU Configuration (MCUCNFx)
    17. 3.17 Software
      1. 3.17.1 SYSCTL Examples
        1. 3.17.1.1 Missing clock detection (MCD) - SINGLE_CORE
        2. 3.17.1.2 XCLKOUT (External Clock Output) Configuration - SINGLE_CORE
      2. 3.17.2 MEMCFG Examples
        1. 3.17.2.1 Correctable & Uncorrectable Memory Error Handling
        2. 3.17.2.2 Shared RAM Management (CPU1) - C28X_DUAL
        3. 3.17.2.3 Shared RAM Management (CPU2) - C28X_DUAL
      3. 3.17.3 NMI Examples
        1. 3.17.3.1 NMI handling - C28X_DUAL
        2. 3.17.3.2 Watchdog Reset - C28X_DUAL
      4. 3.17.4 TIMER Examples
        1. 3.17.4.1 CPU Timers - SINGLE_CORE
        2. 3.17.4.2 CPU Timers - SINGLE_CORE
      5. 3.17.5 WATCHDOG Examples
        1. 3.17.5.1 Watchdog - SINGLE_CORE
    18. 3.18 System Control Registers
      1. 3.18.1  SYSCTRL Base Address Table
      2. 3.18.2  LFU Base Address Table
      3. 3.18.3  CPUTIMER_REGS Registers
      4. 3.18.4  PIE_CTRL_REGS Registers
      5. 3.18.5  WD_REGS Registers
      6. 3.18.6  NMI_INTRUPT_REGS Registers
      7. 3.18.7  XINT_REGS Registers
      8. 3.18.8  SYNC_SOC_REGS Registers
      9. 3.18.9  CPU1_DMA_CLA_SRC_SEL_REGS Registers
      10. 3.18.10 CPU2_DMA_CLA_SRC_SEL_REGS Registers
      11. 3.18.11 DEV_CFG_REGS Registers
      12. 3.18.12 CLK_CFG_REGS Registers
      13. 3.18.13 CPU1_SYS_REGS Registers
      14. 3.18.14 CPU2_SYS_REGS Registers
      15. 3.18.15 CPU1_SYS_STATUS_REGS Registers
      16. 3.18.16 CPU2_SYS_STATUS_REGS Registers
      17. 3.18.17 CPU1_PERIPH_AC_REGS Registers
      18. 3.18.18 CPU2_PERIPH_AC_REGS Registers
      19. 3.18.19 MEM_CFG_REGS Registers
      20. 3.18.20 ACCESS_PROTECTION_REGS Registers
      21. 3.18.21 MEMORY_ERROR_REGS Registers
      22. 3.18.22 ROM_WAIT_STATE_REGS Registers
      23. 3.18.23 TEST_ERROR_REGS Registers
      24. 3.18.24 UID_REGS Registers
      25. 3.18.25 CPU1_LFU_REGS Registers
      26. 3.18.26 CPU2_LFU_REGS Registers
      27. 3.18.27 CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers
      28. 3.18.28 CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers
      29. 3.18.29 CPU2_DMA_CLA_SRC_SEL_REGS Registers
      30. 3.18.30 Register to Driverlib Function Mapping
        1. 3.18.30.1 ASYSCTL Registers to Driverlib Functions
        2. 3.18.30.2 CPUTIMER Registers to Driverlib Functions
        3. 3.18.30.3 MEMCFG Registers to Driverlib Functions
        4. 3.18.30.4 NMI Registers to Driverlib Functions
        5. 3.18.30.5 PIE Registers to Driverlib Functions
        6. 3.18.30.6 SYSCTL Registers to Driverlib Functions
        7. 3.18.30.7 WWD Registers to Driverlib Functions
        8. 3.18.30.8 XINT Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and MPOST Configuration
      2. 4.7.2  Booting CPU2
        1. 4.7.2.1 Boot Up Procedure
        2. 4.7.2.2 IPCBOOTMODE Details
        3. 4.7.2.3 Error IPC Command Table
      3. 4.7.3  Entry Points
      4. 4.7.4  Wait Points
      5. 4.7.5  Secure Flash Boot Mode
        1. 4.7.5.1 Secure Flash CPU1 Linker File Example
      6. 4.7.6  Memory Maps
        1. 4.7.6.1 Boot ROM Memory-Maps
        2. 4.7.6.2 Reserved RAM Memory-Maps
      7. 4.7.7  ROM Tables
      8. 4.7.8  Boot Modes and Loaders
        1. 4.7.8.1 Boot Modes
          1. 4.7.8.1.1 Flash Boot
          2. 4.7.8.1.2 RAM Boot
          3. 4.7.8.1.3 Wait Boot
          4. 4.7.8.1.4 Secure LFU Flash Boot
        2. 4.7.8.2 Bootloaders
          1. 4.7.8.2.1 SCI Boot Mode
          2. 4.7.8.2.2 SPI Boot Mode
          3. 4.7.8.2.3 I2C Boot Mode
          4. 4.7.8.2.4 Parallel Boot Mode
          5. 4.7.8.2.5 CAN Boot Mode
          6. 4.7.8.2.6 CAN-FD Boot Mode
          7. 4.7.8.2.7 USB Boot Mode
          8. 4.7.8.2.8 IPC Message Copy to RAM Boot
          9. 4.7.8.2.9 Firmware Update (FWU) Flash Boot
      9. 4.7.9  GPIO Assignments
      10. 4.7.10 Secure ROM Function APIs
      11. 4.7.11 Clock Initializations
      12. 4.7.12 Boot Status Information
        1. 4.7.12.1 Booting Status
        2. 4.7.12.2 Boot Mode and MPOST (Memory Power On Self-Test) Status
      13. 4.7.13 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
    9. 4.9 Software
      1. 4.9.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
      1. 5.6.1 RAMOPEN
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Examples
        1. 5.8.1.1 Empty DCSM Tool Example
        2. 5.8.1.2 DCSM Memory partitioning Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
      7. 5.9.7 DCSM Registers to Driverlib Functions
  8. 6 Background CRC-32 (BGCRC)
    1. 6.1 Introduction
      1. 6.1.1 BGCRC Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Block Diagram
      4. 6.1.4 Memory Wait States and Memory Map
    2. 6.2 Functional Description
      1. 6.2.1 Data Read Unit
      2. 6.2.2 CRC-32 Compute Unit
      3. 6.2.3 CRC Notification Unit
        1. 6.2.3.1 CPU Interrupt and NMI
      4. 6.2.4 Operating Modes
        1. 6.2.4.1 CRC Mode
        2. 6.2.4.2 Scrub Mode
      5. 6.2.5 BGCRC Watchdog
      6. 6.2.6 Hardware and Software Faults Protection
    3. 6.3 Application of the BGCRC
      1. 6.3.1 Software Configuration
      2. 6.3.2 Decision on Error Response Severity
      3. 6.3.3 Decision of Controller for CLA_CRC
      4. 6.3.4 Execution of Time Critical Code from Wait-Stated Memories
      5. 6.3.5 BGCRC Execution
      6. 6.3.6 Debug/Error Response for BGCRC Errors
      7. 6.3.7 BGCRC Golden CRC-32 Value Computation
    4. 6.4 Software
      1. 6.4.1 BGCRC Examples
        1. 6.4.1.1 BGCRC CPU Interrupt Example
        2. 6.4.1.2 BGCRC Example with Watchdog and Lock
        3. 6.4.1.3 CLA-BGCRC Example in CRC mode
        4. 6.4.1.4 CLA-BGCRC Example in Scrub Mode
    5. 6.5 BGCRC Registers
      1. 6.5.1 BGCRC Base Address Table
      2. 6.5.2 BGCRC_REGS Registers
      3. 6.5.3 BGCRC Registers to Driverlib Functions
  9. 7 Control Law Accelerator (CLA)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 CLA Related Collateral
      3. 7.1.3 Block Diagram
    2. 7.2 CLA Interface
      1. 7.2.1 CLA Memory
      2. 7.2.2 CLA Memory Bus
      3. 7.2.3 Shared Peripherals and EALLOW Protection
      4. 7.2.4 CLA Tasks and Interrupt Vectors
      5. 7.2.5 CLA Software Interrupt to CPU
    3. 7.3 CLA, DMA, and CPU Arbitration
      1. 7.3.1 CLA Message RAM
      2. 7.3.2 CLA Program Memory
      3. 7.3.3 CLA Data Memory
      4. 7.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 7.4 CLA Configuration and Debug
      1. 7.4.1 Building a CLA Application
      2. 7.4.2 Typical CLA Initialization Sequence
      3. 7.4.3 Debugging CLA Code
        1. 7.4.3.1 Software Breakpoint Support (MDEBUGSTOP1)
        2. 7.4.3.2 Legacy Breakpoint Support (MDEBUGSTOP)
      4. 7.4.4 CLA Illegal Opcode Behavior
      5. 7.4.5 Resetting the CLA
    5. 7.5 Pipeline
      1. 7.5.1 Pipeline Overview
      2. 7.5.2 CLA Pipeline Alignment
        1. 7.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       383
        3. 7.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       385
        5. 7.5.2.3 ADC Early Interrupt to CLA Response
      3. 7.5.3 Parallel Instructions
        1. 7.5.3.1 Math Operation with Parallel Load
        2. 7.5.3.2 Multiply with Parallel Add
      4. 7.5.4 CLA Task Execution Latency
    6. 7.6 Software
      1. 7.6.1 CLA Examples
        1. 7.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 7.6.1.2 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        3. 7.6.1.3 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
        4. 7.6.1.4 CLA background nesting task
        5. 7.6.1.5 Controlling PWM output using CLA
        6. 7.6.1.6 Just-in-time ADC sampling with CLA
        7. 7.6.1.7 Optimal offloading of control algorithms to CLA
        8. 7.6.1.8 Handling shared resources across C28x and CLA
    7. 7.7 Instruction Set
      1. 7.7.1 Instruction Descriptions
      2. 7.7.2 Addressing Modes and Encoding
      3. 7.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest [, CNDF]
        11.       MCCNDD 16BitDest [, CNDF]
        12.       MCLRC BGINTM
        13.       MCMP32 MRa, MRb
        14.       MCMPF32 MRa, MRb
        15.       MCMPF32 MRa, #16FHi
        16.       MDEBUGSTOP
        17.       MDEBUGSTOP1
        18.       MEALLOW
        19.       MEDIS
        20.       MEINVF32 MRa, MRb
        21.       MEISQRTF32 MRa, MRb
        22.       MF32TOI16 MRa, MRb
        23.       MF32TOI16R MRa, MRb
        24.       MF32TOI32 MRa, MRb
        25.       MF32TOUI16 MRa, MRb
        26.       MF32TOUI16R MRa, MRb
        27.       MF32TOUI32 MRa, MRb
        28.       MFRACF32 MRa, MRb
        29.       MI16TOF32 MRa, MRb
        30.       MI16TOF32 MRa, mem16
        31.       MI32TOF32 MRa, mem32
        32.       MI32TOF32 MRa, MRb
        33.       MLSL32 MRa, #SHIFT
        34.       MLSR32 MRa, #SHIFT
        35.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        36.       MMAXF32 MRa, MRb
        37.       MMAXF32 MRa, #16FHi
        38.       MMINF32 MRa, MRb
        39.       MMINF32 MRa, #16FHi
        40.       MMOV16 MARx, MRa, #16I
        41.       MMOV16 MARx, mem16
        42.       MMOV16 mem16, MARx
        43.       MMOV16 mem16, MRa
        44.       MMOV32 mem32, MRa
        45.       MMOV32 mem32, MSTF
        46.       MMOV32 MRa, mem32 [, CNDF]
        47.       MMOV32 MRa, MRb [, CNDF]
        48.       MMOV32 MSTF, mem32
        49.       MMOVD32 MRa, mem32
        50.       MMOVF32 MRa, #32F
        51.       MMOVI16 MARx, #16I
        52.       MMOVI32 MRa, #32FHex
        53.       MMOVIZ MRa, #16FHi
        54.       MMOVZ16 MRa, mem16
        55.       MMOVXI MRa, #16FLoHex
        56.       MMPYF32 MRa, MRb, MRc
        57.       MMPYF32 MRa, #16FHi, MRb
        58.       MMPYF32 MRa, MRb, #16FHi
        59.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        60.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        61.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        62.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        63.       MNEGF32 MRa, MRb[, CNDF]
        64.       MNOP
        65.       MOR32 MRa, MRb, MRc
        66.       MRCNDD [CNDF]
        67.       MSETC BGINTM
        68.       MSETFLG FLAG, VALUE
        69.       MSTOP
        70.       MSUB32 MRa, MRb, MRc
        71.       MSUBF32 MRa, MRb, MRc
        72.       MSUBF32 MRa, #16FHi, MRb
        73.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        74.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        75.       MSWAPF MRa, MRb [, CNDF]
        76.       MTESTTF CNDF
        77.       MUI16TOF32 MRa, mem16
        78.       MUI16TOF32 MRa, MRb
        79.       MUI32TOF32 MRa, mem32
        80.       MUI32TOF32 MRa, MRb
        81.       MXOR32 MRa, MRb, MRc
    8. 7.8 CLA Registers
      1. 7.8.1 CLA Base Address Table
      2. 7.8.2 CLA_ONLY_REGS Registers
      3. 7.8.3 CLA_SOFTINT_REGS Registers
      4. 7.8.4 CLA_REGS Registers
      5. 7.8.5 CLA Registers to Driverlib Functions
  10. 8 Configurable Logic Block (CLB)
    1. 8.1  Introduction
      1. 8.1.1 CLB Related Collateral
    2. 8.2  Description
      1. 8.2.1 CLB Clock
    3. 8.3  CLB Input/Output Connection
      1. 8.3.1 Overview
      2. 8.3.2 CLB Input Selection
      3. 8.3.3 CLB Output Selection
      4. 8.3.4 CLB Output Signal Multiplexer
    4. 8.4  CLB Tile
      1. 8.4.1 Static Switch Block
      2. 8.4.2 Counter Block
        1. 8.4.2.1 Counter Description
        2. 8.4.2.2 Counter Operation
        3. 8.4.2.3 Serializer Mode
        4. 8.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 8.4.3 FSM Block
      4. 8.4.4 LUT4 Block
      5. 8.4.5 Output LUT Block
      6. 8.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 8.4.7 High Level Controller (HLC)
        1. 8.4.7.1 High Level Controller Events
        2. 8.4.7.2 High Level Controller Instructions
        3. 8.4.7.3 <Src> and <Dest>
        4. 8.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 8.5  CPU Interface
      1. 8.5.1 Register Description
      2. 8.5.2 Non-Memory Mapped Registers
    6. 8.6  DMA Access
    7. 8.7  CLB Data Export Through SPI RX Buffer
    8. 8.8  CLB Pipeline Mode
    9. 8.9  Software
      1. 8.9.1 CLB Examples
        1. 8.9.1.1  CLB Empty Project
        2. 8.9.1.2  CLB Combinational Logic
        3. 8.9.1.3  CLB GPIO Input Filter
        4. 8.9.1.4  CLB Auxilary PWM
        5. 8.9.1.5  CLB PWM Protection
        6. 8.9.1.6  CLB Event Window
        7. 8.9.1.7  CLB Signal Generator
        8. 8.9.1.8  CLB State Machine
        9. 8.9.1.9  CLB External Signal AND Gate
        10. 8.9.1.10 CLB Timer
        11. 8.9.1.11 CLB Timer Two States
        12. 8.9.1.12 CLB Interrupt Tag
        13. 8.9.1.13 CLB Output Intersect
        14. 8.9.1.14 CLB PUSH PULL
        15. 8.9.1.15 CLB Multi Tile
        16. 8.9.1.16 CLB Tile to Tile Delay
        17. 8.9.1.17 CLB Glue Logic
        18. 8.9.1.18 CLB based One-shot PWM
        19. 8.9.1.19 CLB AOC Control
        20. 8.9.1.20 CLB AOC Release Control
        21. 8.9.1.21 CLB XBARs
        22. 8.9.1.22 CLB AOC Control
        23. 8.9.1.23 CLB Serializer
        24. 8.9.1.24 CLB LFSR
        25. 8.9.1.25 CLB Lock Output Mask
        26. 8.9.1.26 CLB INPUT Pipeline Mode
        27. 8.9.1.27 CLB Clocking and PIPELINE Mode
        28. 8.9.1.28 CLB SPI Data Export
        29. 8.9.1.29 CLB SPI Data Export DMA
        30. 8.9.1.30 CLB Trip Zone Timestamp
        31. 8.9.1.31 CLB CRC
        32. 8.9.1.32 CLB TDM Serial Port
        33. 8.9.1.33 CLB LED Driver
    10. 8.10 CLB Registers
      1. 8.10.1 CLB Base Address Table
      2. 8.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 8.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 8.10.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 8.10.5 CLB Registers to Driverlib Functions
  11. 9 Dual-Clock Comparator (DCC)
    1. 9.1 Introduction
      1. 9.1.1 Features
      2. 9.1.2 Block Diagram
    2. 9.2 Module Operation
      1. 9.2.1 Configuring DCC Counters
      2. 9.2.2 Single-Shot Measurement Mode
      3. 9.2.3 Continuous Monitoring Mode
      4. 9.2.4 Error Conditions
    3. 9.3 Interrupts
    4. 9.4 Software
      1. 9.4.1 DCC Examples
        1. 9.4.1.1 DCC Single shot Clock verification - SINGLE_CORE
        2. 9.4.1.2 DCC Single shot Clock measurement - SINGLE_CORE
        3. 9.4.1.3 DCC Continuous clock monitoring - SINGLE_CORE
    5. 9.5 DCC Registers
      1. 9.5.1 DCC Base Address Table
      2. 9.5.2 DCC_REGS Registers
      3. 9.5.3 DCC Registers to Driverlib Functions
  12. 10Direct Memory Access (DMA)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Architecture
      1. 10.2.1 Peripheral Interrupt Event Trigger Sources
      2. 10.2.2 DMA Bus
    3. 10.3 Address Pointer and Transfer Control
    4. 10.4 Pipeline Timing and Throughput
    5. 10.5 CPU and CLA Arbitration
    6. 10.6 Channel Priority
      1. 10.6.1 Round-Robin Mode
      2. 10.6.2 Channel 1 High-Priority Mode
    7. 10.7 Overrun Detection Feature
    8. 10.8 Software
      1. 10.8.1 DMA Examples
        1. 10.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 10.8.1.2 DMA Transfer Shared Peripheral - C28X_DUAL
        3. 10.8.1.3 DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
        4. 10.8.1.4 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 10.9 DMA Registers
      1. 10.9.1 DMA Base Address Table
      2. 10.9.2 DMA_REGS Registers
      3. 10.9.3 DMA_CH_REGS Registers
      4. 10.9.4 DMA_CLA_SRC_SEL_REGS Registers
      5. 10.9.5 DMA Registers to Driverlib Functions
  13. 11External Memory Interface (EMIF)
    1. 11.1 Introduction
      1. 11.1.1 Purpose of the Peripheral
      2. 11.1.2 EMIF Related Collateral
      3. 11.1.3 Features
        1. 11.1.3.1 Asynchronous Memory Support
        2. 11.1.3.2 Synchronous DRAM Memory Support
      4. 11.1.4 Functional Block Diagram
      5. 11.1.5 Configuring Device Pins
    2. 11.2 EMIF Module Architecture
      1. 11.2.1  EMIF Clock Control
      2. 11.2.2  EMIF Requests
      3. 11.2.3  EMIF Signal Descriptions
      4. 11.2.4  EMIF Signal Multiplexing Control
      5. 11.2.5  SDRAM Controller and Interface
        1. 11.2.5.1  SDRAM Commands
        2. 11.2.5.2  Interfacing to SDRAM
        3. 11.2.5.3  SDRAM Configuration Registers
        4. 11.2.5.4  SDRAM Auto-Initialization Sequence
        5. 11.2.5.5  SDRAM Configuration Procedure
        6. 11.2.5.6  EMIF Refresh Controller
          1. 11.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 11.2.5.7  Self-Refresh Mode
        8. 11.2.5.8  Power-Down Mode
        9. 11.2.5.9  SDRAM Read Operation
        10. 11.2.5.10 SDRAM Write Operations
        11. 11.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 11.2.6  Asynchronous Controller and Interface
        1. 11.2.6.1 Interfacing to Asynchronous Memory
        2. 11.2.6.2 Accessing Larger Asynchronous Memories
        3. 11.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 11.2.6.4 Read and Write Operations in Normal Mode
          1. 11.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 11.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 11.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 11.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 11.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 11.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 11.2.7  Data Bus Parking
      8. 11.2.8  Reset and Initialization Considerations
      9. 11.2.9  Interrupt Support
        1. 11.2.9.1 Interrupt Events
      10. 11.2.10 DMA Event Support
      11. 11.2.11 EMIF Signal Multiplexing
      12. 11.2.12 Memory Map
      13. 11.2.13 Priority and Arbitration
      14. 11.2.14 System Considerations
        1. 11.2.14.1 Asynchronous Request Times
      15. 11.2.15 Power Management
        1. 11.2.15.1 Power Management Using Self-Refresh Mode
        2. 11.2.15.2 Power Management Using Power Down Mode
      16. 11.2.16 Emulation Considerations
    3. 11.3 Example Configuration
      1. 11.3.1 Hardware Interface
      2. 11.3.2 Software Configuration
        1. 11.3.2.1 Configuring the SDRAM Interface
          1. 11.3.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 11.3.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 11.3.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 11.3.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 11.3.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 11.3.2.2 Configuring the Flash Interface
          1. 11.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    4. 11.4 Software
      1. 11.4.1 EMIF Examples
        1. 11.4.1.1 Pin setup for EMIF module accessing ASRAM.
        2. 11.4.1.2 EMIF1 ASYNC module accessing 16bit ASRAM.
        3. 11.4.1.3 EMIF1 module accessing 16bit ASRAM as code memory.
        4. 11.4.1.4 EMIF1 module accessing 16bit SDRAM using memcpy_fast_far().
        5. 11.4.1.5 EMIF1 module accessing 16bit SDRAM then puts into Self Refresh mode before entering Low Power Mode.
        6. 11.4.1.6 EMIF1 module accessing 32bit SDRAM using DMA.
        7. 11.4.1.7 EMIF1 module accessing 16bit SDRAM using alternate address mapping.
    5. 11.5 EMIF Registers
      1. 11.5.1 EMIF Base Address Table
      2. 11.5.2 EMIF_REGS Registers
      3. 11.5.3 EMIF1_CONFIG_REGS Registers
      4. 11.5.4 EMIF Registers to Driverlib Functions
  14. 12Flash Module
    1. 12.1  Introduction to Flash and OTP Memory
      1. 12.1.1 FLASH Related Collateral
      2. 12.1.2 Features
      3. 12.1.3 Flash Tools
      4. 12.1.4 Default Flash Configuration
    2. 12.2  Flash Bank, OTP, and Pump
    3. 12.3  Flash Wrapper
    4. 12.4  Flash and OTP Memory Performance
    5. 12.5  Flash Read Interface
      1. 12.5.1 C28x-Flash Read Interface
        1. 12.5.1.1 Standard Read Mode
        2. 12.5.1.2 Prefetch Mode
        3. 12.5.1.3 Data Cache
        4. 12.5.1.4 Flash Read Operation
    6. 12.6  Flash Erase and Program
      1. 12.6.1 Flash Controller Access Semaphore
      2. 12.6.2 Erase
      3. 12.6.3 Program
      4. 12.6.4 Verify
    7. 12.7  Error Correction Code (ECC) Protection
      1. 12.7.1 Single-Bit Data Error
      2. 12.7.2 Uncorrectable Error
      3. 12.7.3 Mechanism to Check the Correctness of ECC Logic
    8. 12.8  Reserved Locations Within Flash and OTP
    9. 12.9  Migrating an Application from RAM to Flash
    10. 12.10 Procedure to Change the Flash Control Registers
    11. 12.11 Software
      1. 12.11.1 FLASH Examples
        1. 12.11.1.1 Flash Programming with 512-bit AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
        2. 12.11.1.2 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
        3. 12.11.1.3 Flash Programming with 512-bit AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
        4. 12.11.1.4 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly - C28X_DUAL
    12. 12.12 Flash Registers
      1. 12.12.1 FLASH Base Address Table
      2. 12.12.2 FLASH_CTRL_REGS Registers
      3. 12.12.3 FLASH_ECC_REGS Registers
      4. 12.12.4 FLASH Registers to Driverlib Functions
  15. 13Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 13.1 Introduction
      1. 13.1.1 ERAD Related Collateral
    2. 13.2 Enhanced Bus Comparator Unit
      1. 13.2.1 Enhanced Bus Comparator Unit Operations
      2. 13.2.2 Event Masking and Exporting
    3. 13.3 System Event Counter Unit
      1. 13.3.1 System Event Counter Modes
        1. 13.3.1.1 Counting Active Levels Versus Edges
        2. 13.3.1.2 Max Mode
        3. 13.3.1.3 Cumulative Mode
        4. 13.3.1.4 Input Signal Selection
      2. 13.3.2 Reset on Event
      3. 13.3.3 Operation Conditions
    4. 13.4 ERAD Ownership, Initialization and Reset
    5. 13.5 ERAD Programming Sequence
      1. 13.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 13.5.2 Timer and Counter Programming Sequence
    6. 13.6 Cyclic Redundancy Check Unit
      1. 13.6.1 CRC Unit Qualifier
      2. 13.6.2 CRC Unit Programming Sequence
    7. 13.7 Program Counter Trace
      1. 13.7.1 Functional Block Diagram
      2. 13.7.2 Trace Qualification Modes
      3. 13.7.3 Trace Memory
      4. 13.7.4 Trace Input Signal Conditioning
      5. 13.7.5 PC Trace Software Operation
      6. 13.7.6 Trace Operation in Debug Mode
    8. 13.8 Software
      1. 13.8.1 ERAD Examples
        1. 13.8.1.1  ERAD Profiling Interrupts
        2. 13.8.1.2  ERAD Profile Function
        3. 13.8.1.3  ERAD Profile Function
        4. 13.8.1.4  ERAD HWBP Monitor Program Counter
        5. 13.8.1.5  ERAD HWBP Monitor Program Counter
        6. 13.8.1.6  ERAD Profile Function
        7. 13.8.1.7  ERAD HWBP Stack Overflow Detection
        8. 13.8.1.8  ERAD HWBP Stack Overflow Detection
        9. 13.8.1.9  ERAD Stack Overflow
        10. 13.8.1.10 ERAD Profile Interrupts CLA
        11. 13.8.1.11 ERAD Profiling Interrupts
        12. 13.8.1.12 ERAD Profiling Interrupts
        13. 13.8.1.13 ERAD MEMORY ACCESS RESTRICT
        14. 13.8.1.14 ERAD INTERRUPT ORDER
        15. 13.8.1.15 ERAD AND CLB
        16. 13.8.1.16 ERAD PWM PROTECTION
    9. 13.9 ERAD Registers
      1. 13.9.1 ERAD Base Address Table
      2. 13.9.2 ERAD_GLOBAL_REGS Registers
      3. 13.9.3 ERAD_HWBP_REGS Registers
      4. 13.9.4 ERAD_COUNTER_REGS Registers
      5. 13.9.5 ERAD_CRC_GLOBAL_REGS Registers
      6. 13.9.6 ERAD_CRC_REGS Registers
      7. 13.9.7 PCTRACE_REGS Registers
      8. 13.9.8 PCTRACE_BUFFER_REGS Registers
      9. 13.9.9 ERAD Registers to Driverlib Functions
  16. 14General-Purpose Input/Output (GPIO)
    1. 14.1  Introduction
      1. 14.1.1 GPIO Related Collateral
    2. 14.2  Configuration Overview
    3. 14.3  Digital Inputs on ADC Pins (AIOs)
    4. 14.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 14.5  Digital General-Purpose I/O Control
    6. 14.6  Input Qualification
      1. 14.6.1 No Synchronization (Asynchronous Input)
      2. 14.6.2 Synchronization to SYSCLKOUT Only
      3. 14.6.3 Qualification Using a Sampling Window
    7. 14.7  USB Signals
    8. 14.8  GPIO and Peripheral Muxing
      1. 14.8.1 GPIO Muxing
      2. 14.8.2 Peripheral Muxing
    9. 14.9  Internal Pullup Configuration Requirements
    10. 14.10 Software
      1. 14.10.1 GPIO Examples
        1. 14.10.1.1 Device GPIO Toggle - SINGLE_CORE
        2. 14.10.1.2 XINT/XBAR example - SINGLE_CORE
      2. 14.10.2 LED Examples
        1. 14.10.2.1 LED Blinky Example - MULTI_CORE
        2. 14.10.2.2 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
        3. 14.10.2.3 LED Blinky example - SINGLE_CORE
        4. 14.10.2.4 LED Blinky Example (CPU1|CPU2|CPU3) - MULTI_CORE
        5. 14.10.2.5 LED Blinky Example (CPU2) - MULTI_CORE
        6. 14.10.2.6 LED Blinky Example (CPU3) - MULTI_CORE
    11. 14.11 GPIO Registers
      1. 14.11.1 GPIO Base Address Table
      2. 14.11.2 GPIO_CTRL_REGS Registers
      3. 14.11.3 GPIO_DATA_REGS Registers
      4. 14.11.4 GPIO_DATA_READ_REGS Registers
      5. 14.11.5 GPIO Registers to Driverlib Functions
  17. 15Interprocessor Communication (IPC)
    1. 15.1 Introduction
    2. 15.2 Message RAMs
    3. 15.3 IPC Flags and Interrupts
    4. 15.4 IPC Command Registers
    5. 15.5 Free-Running Counter
    6. 15.6 IPC Communication Protocol
    7. 15.7 Software
      1. 15.7.1 IPC Examples
        1. 15.7.1.1 IPC basic message passing example with interrupt - MULTI_CORE
        2. 15.7.1.2 IPC basic message passing example with interrupt - MULTI_CORE
        3. 15.7.1.3 IPC basic message passing example with interrupt - MULTI_CORE
        4. 15.7.1.4 IPC basic message passing example with interrupt - MULTI_CORE
    8. 15.8 IPC Registers
      1. 15.8.1 IPC Base Address Table
      2. 15.8.2 CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers
      3. 15.8.3 CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers
      4. 15.8.4 IPC Registers to Driverlib Functions
  18. 16Crossbar (X-BAR)
    1. 16.1 Input X-BAR, ICL XBAR, MINDB XBAR, and CLB Input X-BAR
      1. 16.1.1 CLB Input X-BAR
      2. 16.1.2 ICL and MINDB X-BAR
    2. 16.2 ePWM , CLB, and GPIO Output X-BAR
      1. 16.2.1 ePWM X-BAR
        1. 16.2.1.1 ePWM X-BAR Architecture
      2. 16.2.2 CLB X-BAR
        1. 16.2.2.1 CLB X-BAR Architecture
      3. 16.2.3 GPIO Output X-BAR
        1. 16.2.3.1 GPIO Output X-BAR Architecture
      4. 16.2.4 CLB Output X-BAR
        1. 16.2.4.1 CLB Output X-BAR Architecture
      5. 16.2.5 X-BAR Flags
    3. 16.3 XBAR Registers
      1. 16.3.1  XBAR Base Address Table
      2. 16.3.2  EPWM_XBAR_REGS Registers
      3. 16.3.3  INPUT_XBAR_REGS Registers
      4. 16.3.4  XBAR_REGS Registers
      5. 16.3.5  MINDB_XBAR_REGS Registers
      6. 16.3.6  ICL_XBAR_REGS Registers
      7. 16.3.7  CLB_XBAR_REGS Registers
      8. 16.3.8  OUTPUT_XBAR_EXT64_REGS Registers
      9. 16.3.9  OUTPUT_XBAR_REGS Registers
      10. 16.3.10 Register to Driverlib Function Mapping
        1. 16.3.10.1 EPWMXBAR Registers to Driverlib Functions
        2. 16.3.10.2 INPUTXBAR Registers to Driverlib Functions
        3. 16.3.10.3 XBAR Registers to Driverlib Functions
        4. 16.3.10.4 MINDBXBAR Registers to Driverlib Functions
        5. 16.3.10.5 ICLXBAR Registers to Driverlib Functions
        6. 16.3.10.6 CLBXBAR Registers to Driverlib Functions
        7. 16.3.10.7 OUTPUTXBAR Registers to Driverlib Functions
  19. 17Analog Subsystem
    1. 17.1 Introduction
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
    2. 17.2 Optimizing Power-Up Time
    3. 17.3 Digital Inputs on ADC Pins (AIOs)
    4. 17.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 17.5 Analog Subsystem Registers
      1. 17.5.1 ASBSYS Base Address Table
      2. 17.5.2 ANALOG_SUBSYS_REGS Registers
  20. 18Analog-to-Digital Converter (ADC)
    1. 18.1  Introduction
      1. 18.1.1 ADC Related Collateral
      2. 18.1.2 Features
      3. 18.1.3 Block Diagram
    2. 18.2  ADC Configurability
      1. 18.2.1 Clock Configuration
      2. 18.2.2 Resolution
      3. 18.2.3 Voltage Reference
        1. 18.2.3.1 External Reference Mode
        2. 18.2.3.2 Internal Reference Mode
        3. 18.2.3.3 Ganged References
        4. 18.2.3.4 Selecting Reference Mode
      4. 18.2.4 Signal Mode
      5. 18.2.5 Expected Conversion Results
      6. 18.2.6 Interpreting Conversion Results
    3. 18.3  SOC Principle of Operation
      1. 18.3.1 SOC Configuration
      2. 18.3.2 Trigger Operation
        1. 18.3.2.1 Global Software Trigger
        2. 18.3.2.2 Trigger Repeaters
          1. 18.3.2.2.1 Oversampling Mode
          2. 18.3.2.2.2 Undersampling Mode
          3. 18.3.2.2.3 Trigger Phase Delay
          4. 18.3.2.2.4 Re-trigger Spread
          5. 18.3.2.2.5 Trigger Repeater Configuration
            1. 18.3.2.2.5.1 Register Shadow Updates
          6. 18.3.2.2.6 Re-Trigger Logic
          7. 18.3.2.2.7 Multi-Path Triggering Behavior
      3. 18.3.3 ADC Acquisition (Sample and Hold) Window
      4. 18.3.4 ADC Input Models
      5. 18.3.5 Channel Selection
        1. 18.3.5.1 External Channel Selection
          1. 18.3.5.1.1 External Channel Selection Timing
    4. 18.4  SOC Configuration Examples
      1. 18.4.1 Single Conversion from ePWM Trigger
      2. 18.4.2 Oversampled Conversion from ePWM Trigger
      3. 18.4.3 Multiple Conversions from CPU Timer Trigger
      4. 18.4.4 Software Triggering of SOCs
    5. 18.5  ADC Conversion Priority
    6. 18.6  Burst Mode
      1. 18.6.1 Burst Mode Example
      2. 18.6.2 Burst Mode Priority Example
    7. 18.7  EOC and Interrupt Operation
      1. 18.7.1 Interrupt Overflow
      2. 18.7.2 Continue to Interrupt Mode
      3. 18.7.3 Early Interrupt Configuration Mode
    8. 18.8  Post-Processing Blocks
      1. 18.8.1 PPB Offset Correction
      2. 18.8.2 PPB Error Calculation
      3. 18.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 18.8.4 PPB Sample Delay Capture
      5. 18.8.5 PPB Oversampling
        1. 18.8.5.1 Accumulation, Minimum, Maximum, and Average Functions
        2. 18.8.5.2 Outlier Rejection
    9. 18.9  Result Safety Checker
      1. 18.9.1 Result Safety Checker Operation
      2. 18.9.2 Result Safety Checker Interrupts and Events
    10. 18.10 Opens/Shorts Detection Circuit (OSDETECT)
      1. 18.10.1 Implementation
      2. 18.10.2 Detecting an Open Input Pin
      3. 18.10.3 Detecting a Shorted Input Pin
    11. 18.11 Power-Up Sequence
    12. 18.12 ADC Calibration
      1. 18.12.1 ADC Zero Offset Calibration
    13. 18.13 ADC Timings
      1. 18.13.1 ADC Timing Diagrams
      2. 18.13.2 Post-Processing Block Timings
    14. 18.14 Additional Information
      1. 18.14.1 Ensuring Synchronous Operation
        1. 18.14.1.1 Basic Synchronous Operation
        2. 18.14.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 18.14.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 18.14.1.4 Synchronous Operation with Different Resolutions
        5. 18.14.1.5 Non-overlapping Conversions
      2. 18.14.2 Choosing an Acquisition Window Duration
      3. 18.14.3 Achieving Simultaneous Sampling
      4. 18.14.4 Result Register Mapping
      5. 18.14.5 Internal Temperature Sensor
      6. 18.14.6 Designing an External Reference Circuit
      7. 18.14.7 ADC-DAC Loopback Testing
      8. 18.14.8 Internal Test Mode
      9. 18.14.9 ADC Gain and Offset Calibration
    15. 18.15 Software
      1. 18.15.1 ADC Examples
        1. 18.15.1.1  ADC Software Triggering - SINGLE_CORE
        2. 18.15.1.2  ADC ePWM Triggering - SINGLE_CORE
        3. 18.15.1.3  ADC Temperature Sensor Conversion - SINGLE_CORE
        4. 18.15.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync) - SINGLE_CORE
        5. 18.15.1.5  ADC Continuous Triggering (adc_soc_continuous) - SINGLE_CORE
        6. 18.15.1.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) - SINGLE_CORE
        7. 18.15.1.7  ADC PPB Offset (adc_ppb_offset) - SINGLE_CORE
        8. 18.15.1.8  ADC PPB Limits (adc_ppb_limits) - SINGLE_CORE
        9. 18.15.1.9  ADC PPB Delay Capture (adc_ppb_delay) - SINGLE_CORE
        10. 18.15.1.10 ADC ePWM Triggering Multiple SOC - SINGLE_CORE
        11. 18.15.1.11 ADC Burst Mode - SINGLE_CORE
        12. 18.15.1.12 ADC Burst Mode Oversampling - SINGLE_CORE
        13. 18.15.1.13 ADC SOC Oversampling - SINGLE_CORE
        14. 18.15.1.14 ADC PPB PWM trip (adc_ppb_pwm_trip) - SINGLE_CORE
        15. 18.15.1.15 ADC Trigger Repeater Oversampling - SINGLE_CORE
        16. 18.15.1.16 ADC Trigger Repeater Undersampling - SINGLE_CORE
        17. 18.15.1.17 ADC Safety Checker - SINGLE_CORE
    16. 18.16 ADC Registers
      1. 18.16.1 ADC Base Address Table
      2. 18.16.2 ADC_RESULT_REGS Registers
      3. 18.16.3 ADC_REGS Registers
      4. 18.16.4 ADC_SAFECHECK_INTEVT_REGS Registers
      5. 18.16.5 ADC_SAFECHECK_REGS Registers
      6. 18.16.6 ADC Registers to Driverlib Functions
  21. 19Buffered Digital-to-Analog Converter (DAC)
    1. 19.1 Introduction
      1. 19.1.1 DAC Related Collateral
      2. 19.1.2 Features
      3. 19.1.3 Block Diagram
    2. 19.2 Using the DAC
      1. 19.2.1 Initialization Sequence
      2. 19.2.2 DAC Offset Adjustment
      3. 19.2.3 EPWMSYNCPER Signal
    3. 19.3 Lock Registers
    4. 19.4 Software
      1. 19.4.1 DAC Examples
        1. 19.4.1.1 Buffered DAC Enable - SINGLE_CORE
        2. 19.4.1.2 Buffered DAC Random - SINGLE_CORE
    5. 19.5 DAC Registers
      1. 19.5.1 DAC Base Address Table
      2. 19.5.2 DAC_REGS Registers
      3. 19.5.3 DAC Registers to Driverlib Functions
  22. 20Comparator Subsystem (CMPSS)
    1. 20.1 Introduction
      1. 20.1.1 CMPSS Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Block Diagram
    2. 20.2 Comparator
    3. 20.3 Reference DAC
    4. 20.4 Ramp Generator
      1. 20.4.1 Ramp Generator Overview
      2. 20.4.2 Ramp Generator Behavior
      3. 20.4.3 Ramp Generator Behavior at Corner Cases
    5. 20.5 Digital Filter
      1. 20.5.1 Filter Initialization Sequence
    6. 20.6 Using the CMPSS
      1. 20.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 20.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 20.6.3 Calibrating the CMPSS
      4. 20.6.4 Enabling and Disabling the CMPSS Clock
    7. 20.7 Software
      1. 20.7.1 CMPSS Examples
        1. 20.7.1.1 CMPSS Asynchronous Trip - SINGLE_CORE
        2. 20.7.1.2 CMPSS Digital Filter Configuration - SINGLE_CORE
    8. 20.8 CMPSS Registers
      1. 20.8.1 CMPSS Base Address Table
      2. 20.8.2 CMPSS_REGS Registers
      3. 20.8.3 CMPSS Registers to Driverlib Functions
  23. 21Enhanced Capture (eCAP) and High Resolution Capture (HRCAP)
    1. 21.1  Introduction
      1. 21.1.1 Features
      2. 21.1.2 ECAP Related Collateral
    2. 21.2  Description
    3. 21.3  Configuring Device Pins for the eCAP
    4. 21.4  Capture and APWM Operating Mode
    5. 21.5  Capture Mode Description
      1. 21.5.1  Event Prescaler
      2. 21.5.2  Glitch Filter
      3. 21.5.3  Edge Polarity Select and Qualifier
      4. 21.5.4  Continuous/One-Shot Control
      5. 21.5.5  32-Bit Counter and Phase Control
      6. 21.5.6  CAP1-CAP4 Registers
      7. 21.5.7  eCAP Synchronization
        1. 21.5.7.1 Example 1 - Using SWSYNC with ECAP Module
      8. 21.5.8  Interrupt Control
      9. 21.5.9  DMA Interrupt
      10. 21.5.10 ADC SOC Event
      11. 21.5.11 Shadow Load and Lockout Control
      12. 21.5.12 APWM Mode Operation
      13. 21.5.13 Signal Monitoring Unit
        1. 21.5.13.1 Pulse Width and Period Monitoring
        2. 21.5.13.2 Edge Monitoring
    6. 21.6  Application of the eCAP Module
      1. 21.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 21.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 21.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 21.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 21.7  Application of the APWM Mode
      1. 21.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 21.8  High Resolution Capture (HRCAP) Module
      1. 21.8.1 Introduction
        1. 21.8.1.1 HRCAP Related Collateral
        2. 21.8.1.2 Features
        3. 21.8.1.3 Description
      2. 21.8.2 Operational Details
        1. 21.8.2.1 HRCAP Clocking
        2. 21.8.2.2 HRCAP Initialization Sequence
        3. 21.8.2.3 HRCAP Interrupts
        4. 21.8.2.4 HRCAP Calibration
          1. 21.8.2.4.1 Applying the Scale Factor
      3. 21.8.3 Known Exceptions
    9. 21.9  Software
      1. 21.9.1 ECAP Examples
        1. 21.9.1.1 eCAP APWM Example - SINGLE_CORE
        2. 21.9.1.2 eCAP Capture PWM Example - SINGLE_CORE
        3. 21.9.1.3 eCAP APWM Phase-shift Example - SINGLE_CORE
      2. 21.9.2 HRCAP Examples
        1. 21.9.2.1 HRCAP Capture and Calibration Example - SINGLE_CORE
    10. 21.10 eCAP Registers
      1. 21.10.1 ECAP Base Address Table
      2. 21.10.2 ECAP_REGS Registers
      3. 21.10.3 ECAP_SIGNAL_MONITORING Registers
      4. 21.10.4 ECAP Registers to Driverlib Functions
    11. 21.11 HRCAP Registers
      1. 21.11.1 HRCAP Base Address Table
      2. 21.11.2 HRCAP_REGS Registers
      3. 21.11.3 HRCAP Registers to Driverlib Functions
  24. 22Enhanced Pulse Width Modulator (ePWM)
    1. 22.1  Introduction
      1. 22.1.1 EPWM Related Collateral
      2. 22.1.2 Submodule Overview
    2. 22.2  Configuring Device Pins
    3. 22.3  ePWM Modules Overview
    4. 22.4  Time-Base (TB) Submodule
      1. 22.4.1 Purpose of the Time-Base Submodule
      2. 22.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 22.4.3 Calculating PWM Period and Frequency
        1. 22.4.3.1 Time-Base Period Shadow Register
        2. 22.4.3.2 Time-Base Clock Synchronization
        3. 22.4.3.3 Time-Base Counter Synchronization
        4. 22.4.3.4 ePWM SYNC Selection
      4. 22.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 22.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 22.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 22.4.7 Global Load
        1. 22.4.7.1 Global Load Pulse Pre-Scalar
        2. 22.4.7.2 One-Shot Load Mode
        3. 22.4.7.3 One-Shot Sync Mode
    5. 22.5  Counter-Compare (CC) Submodule
      1. 22.5.1 Purpose of the Counter-Compare Submodule
      2. 22.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 22.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 22.5.4 Count Mode Timing Waveforms
    6. 22.6  Action-Qualifier (AQ) Submodule
      1. 22.6.1 Purpose of the Action-Qualifier Submodule
      2. 22.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 22.6.3 Action-Qualifier Event Priority
      4. 22.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 22.6.5 Configuration Requirements for Common Waveforms
    7. 22.7  XCMP Complex Waveform Generator Mode
      1. 22.7.1 XCMP Allocation to CMPA and CMPB
      2. 22.7.2 XCMP Shadow Buffers
      3. 22.7.3 XCMP Operation
    8. 22.8  Dead-Band Generator (DB) Submodule
      1. 22.8.1 Purpose of the Dead-Band Submodule
      2. 22.8.2 Dead-band Submodule Additional Operating Modes
      3. 22.8.3 Operational Highlights for the Dead-Band Submodule
    9. 22.9  PWM Chopper (PC) Submodule
      1. 22.9.1 Purpose of the PWM Chopper Submodule
      2. 22.9.2 Operational Highlights for the PWM Chopper Submodule
      3. 22.9.3 Waveforms
        1. 22.9.3.1 One-Shot Pulse
        2. 22.9.3.2 Duty Cycle Control
    10. 22.10 Trip-Zone (TZ) Submodule
      1. 22.10.1 Purpose of the Trip-Zone Submodule
      2. 22.10.2 Operational Highlights for the Trip-Zone Submodule
        1. 22.10.2.1 Trip-Zone Configurations
      3. 22.10.3 Generating Trip Event Interrupts
    11. 22.11 Diode Emulation (DE) Submodule
      1. 22.11.1 DEACTIVE Mode
      2. 22.11.2 Exiting DE Mode
      3. 22.11.3 Re-Entering DE Mode
      4. 22.11.4 DE Monitor
    12. 22.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
      1. 22.12.1 Minimum Dead-Band (MINDB)
      2. 22.12.2 Illegal Combo Logic (ICL)
    13. 22.13 Event-Trigger (ET) Submodule
      1. 22.13.1 Operational Overview of the ePWM Event-Trigger Submodule
    14. 22.14 Digital Compare (DC) Submodule
      1. 22.14.1 Purpose of the Digital Compare Submodule
      2. 22.14.2 Enhanced Trip Action Using CMPSS
      3. 22.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 22.14.4 Operation Highlights of the Digital Compare Submodule
        1. 22.14.4.1 Digital Compare Events
        2. 22.14.4.2 Event Filtering
        3. 22.14.4.3 Valley Switching
        4. 22.14.4.4 Event Detection
          1. 22.14.4.4.1 Input Signal Detection
          2. 22.14.4.4.2 MIN and MAX Detection Circuit
    15. 22.15 ePWM Crossbar (X-BAR)
    16. 22.16 Applications to Power Topologies
      1. 22.16.1  Overview of Multiple Modules
      2. 22.16.2  Key Configuration Capabilities
      3. 22.16.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 22.16.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 22.16.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 22.16.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 22.16.7  Practical Applications Using Phase Control Between PWM Modules
      8. 22.16.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 22.16.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 22.16.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 22.16.11 Controlling H-Bridge LLC Resonant Converter
    17. 22.17 Register Lock Protection
    18. 22.18 High-Resolution Pulse Width Modulator (HRPWM)
      1. 22.18.1 Operational Description of HRPWM
        1. 22.18.1.1 Controlling the HRPWM Capabilities
        2. 22.18.1.2 HRPWM Source Clock
        3. 22.18.1.3 Configuring the HRPWM
        4. 22.18.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 22.18.1.5 Principle of Operation
          1. 22.18.1.5.1 Edge Positioning
          2. 22.18.1.5.2 Scaling Considerations
          3. 22.18.1.5.3 Duty Cycle Range Limitation
          4. 22.18.1.5.4 High-Resolution Period
            1. 22.18.1.5.4.1 High-Resolution Period Configuration
        6. 22.18.1.6 Deadband High-Resolution Operation
        7. 22.18.1.7 Scale Factor Optimizing Software (SFO)
        8. 22.18.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 22.18.1.8.1 #Defines for HRPWM Header Files
          2. 22.18.1.8.2 Implementing a Simple Buck Converter
            1. 22.18.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 22.18.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 22.18.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 22.18.1.8.3.1 PWM DAC Function Initialization Code
            2. 22.18.1.8.3.2 PWM DAC Function Run-Time Code
      2. 22.18.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 22.18.2.1 Scale Factor Optimizer Function - int SFO()
        2. 22.18.2.2 Software Usage
          1. 22.18.2.2.1 A Sample of How to Add "Include" Files
          2.        1198
          3. 22.18.2.2.2 Declaring an Element
          4.        1200
          5. 22.18.2.2.3 Initializing With a Scale Factor Value
          6.        1202
          7. 22.18.2.2.4 SFO Function Calls
    19. 22.19 Software
      1. 22.19.1 EPWM Examples
        1. 22.19.1.1  ePWM Trip Zone - SINGLE_CORE
        2. 22.19.1.2  ePWM Up Down Count Action Qualifier - SINGLE_CORE
        3. 22.19.1.3  ePWM Synchronization - SINGLE_CORE
        4. 22.19.1.4  ePWM Digital Compare - SINGLE_CORE
        5. 22.19.1.5  ePWM Digital Compare Event Filter Blanking Window - SINGLE_CORE
        6. 22.19.1.6  ePWM Valley Switching - SINGLE_CORE
        7. 22.19.1.7  ePWM Digital Compare Edge Filter - SINGLE_CORE
        8. 22.19.1.8  ePWM Deadband - SINGLE_CORE
        9. 22.19.1.9  ePWM DMA - SINGLE_CORE
        10. 22.19.1.10 ePWM Chopper - SINGLE_CORE
        11. 22.19.1.11 EPWM Configure Signal - SINGLE_CORE
        12. 22.19.1.12 Realization of Monoshot mode - SINGLE_CORE
        13. 22.19.1.13 EPWM Action Qualifier (epwm_up_aq) - SINGLE_CORE
        14. 22.19.1.14 ePWM XCMP Mode - SINGLE_CORE
        15. 22.19.1.15 ePWM Event Detection - SINGLE_CORE
      2. 22.19.2 HRPWM Examples
        1. 22.19.2.1 HRPWM Duty Control with SFO
        2. 22.19.2.2 HRPWM Slider
        3. 22.19.2.3 HRPWM Period Control
        4. 22.19.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 22.19.2.5 HRPWM Slider Test
        6. 22.19.2.6 HRPWM Duty Up Count
        7. 22.19.2.7 HRPWM Period Up-Down Count
    20. 22.20 ePWM Registers
      1. 22.20.1 EPWM Base Address Table
      2. 22.20.2 EPWM_REGS Registers
      3. 22.20.3 EPWM_XCMP_REGS Registers
      4. 22.20.4 DE_REGS Registers
      5. 22.20.5 MINDB_LUT_REGS Registers
      6. 22.20.6 HRPWMCAL_REGS Registers
      7. 22.20.7 Register to Driverlib Function Mapping
        1. 22.20.7.1 EPWM Registers to Driverlib Functions
        2. 22.20.7.2 HRPWM Registers to Driverlib Functions
        3. 22.20.7.3 HRPWMCAL Registers to Driverlib Functions
  25. 23Enhanced Quadrature Encoder Pulse (eQEP)
    1. 23.1  Introduction
      1. 23.1.1 EQEP Related Collateral
    2. 23.2  Configuring Device Pins
    3. 23.3  Description
      1. 23.3.1 EQEP Inputs
      2. 23.3.2 Functional Description
      3. 23.3.3 eQEP Memory Map
    4. 23.4  Quadrature Decoder Unit (QDU)
      1. 23.4.1 Position Counter Input Modes
        1. 23.4.1.1 Quadrature Count Mode
        2. 23.4.1.2 Direction-Count Mode
        3. 23.4.1.3 Up-Count Mode
        4. 23.4.1.4 Down-Count Mode
      2. 23.4.2 eQEP Input Polarity Selection
      3. 23.4.3 Position-Compare Sync Output
    5. 23.5  Position Counter and Control Unit (PCCU)
      1. 23.5.1 Position Counter Operating Modes
        1. 23.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 23.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 23.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 23.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 23.5.2 Position Counter Latch
        1. 23.5.2.1 Index Event Latch
        2. 23.5.2.2 Strobe Event Latch
      3. 23.5.3 Position Counter Initialization
      4. 23.5.4 eQEP Position-compare Unit
    6. 23.6  eQEP Edge Capture Unit
    7. 23.7  eQEP Watchdog
    8. 23.8  eQEP Unit Timer Base
    9. 23.9  QMA Module
      1. 23.9.1 Modes of Operation
        1. 23.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 23.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 23.9.2 Interrupt and Error Generation
    10. 23.10 eQEP Interrupt Structure
    11. 23.11 Software
      1. 23.11.1 EQEP Examples
        1. 23.11.1.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        2. 23.11.1.2 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
    12. 23.12 eQEP Registers
      1. 23.12.1 EQEP Base Address Table
      2. 23.12.2 EQEP_REGS Registers
      3. 23.12.3 EQEP Registers to Driverlib Functions
  26. 24Sigma Delta Filter Module (SDFM)
    1. 24.1  Introduction
      1. 24.1.1 SDFM Related Collateral
      2. 24.1.2 Features
      3. 24.1.3 Block Diagram
    2. 24.2  Configuring Device Pins
    3. 24.3  Input Qualification
    4. 24.4  Input Control Unit
    5. 24.5  SDFM Clock Control
    6. 24.6  Sinc Filter
      1. 24.6.1 Data Rate and Latency of the Sinc Filter
    7. 24.7  Data (Primary) Filter Unit
      1. 24.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 24.7.2 Data FIFO
      3. 24.7.3 SDSYNC Event
    8. 24.8  Comparator (Secondary) Filter Unit
      1. 24.8.1 Higher Threshold (HLT) Comparators
      2. 24.8.2 Lower Threshold (LLT) Comparators
      3. 24.8.3 Digital Filter
    9. 24.9  Theoretical SDFM Filter Output
    10. 24.10 Interrupt Unit
      1. 24.10.1 SDFM (SDyERR) Interrupt Sources
      2. 24.10.2 Data Ready (DRINT) Interrupt Sources
    11. 24.11 Software
      1. 24.11.1 SDFM Examples
        1. 24.11.1.1 SDFM Filter Sync CPU
        2. 24.11.1.2 SDFM Filter Sync CLA
        3. 24.11.1.3 SDFM Filter Sync DMA
        4. 24.11.1.4 SDFM PWM Sync
        5. 24.11.1.5 SDFM Type 1 Filter FIFO
        6. 24.11.1.6 SDFM Filter Sync CLA
    12. 24.12 SDFM Registers
      1. 24.12.1 SDFM Base Address Table
      2. 24.12.2 SDFM_REGS Registers
      3. 24.12.3 SDFM Registers to Driverlib Functions
  27. 25Controller Area Network (CAN)
    1. 25.1  Introduction
      1. 25.1.1 DCAN Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
        1. 25.1.3.1 CAN Core
        2. 25.1.3.2 Message Handler
        3. 25.1.3.3 Message RAM
        4. 25.1.3.4 Registers and Message Object Access (IFx)
    2. 25.2  Functional Description
      1. 25.2.1 Configuring Device Pins
      2. 25.2.2 Address/Data Bus Bridge
    3. 25.3  Operating Modes
      1. 25.3.1 Initialization
      2. 25.3.2 CAN Message Transfer (Normal Operation)
        1. 25.3.2.1 Disabled Automatic Retransmission
        2. 25.3.2.2 Auto-Bus-On
      3. 25.3.3 Test Modes
        1. 25.3.3.1 Silent Mode
        2. 25.3.3.2 Loopback Mode
        3. 25.3.3.3 External Loopback Mode
        4. 25.3.3.4 Loopback Combined with Silent Mode
    4. 25.4  Multiple Clock Source
    5. 25.5  Interrupt Functionality
      1. 25.5.1 Message Object Interrupts
      2. 25.5.2 Status Change Interrupts
      3. 25.5.3 Error Interrupts
      4. 25.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 25.5.5 Interrupt Topologies
    6. 25.6  DMA Functionality
    7. 25.7  Parity Check Mechanism
      1. 25.7.1 Behavior on Parity Error
    8. 25.8  Debug Mode
    9. 25.9  Module Initialization
    10. 25.10 Configuration of Message Objects
      1. 25.10.1 Configuration of a Transmit Object for Data Frames
      2. 25.10.2 Configuration of a Transmit Object for Remote Frames
      3. 25.10.3 Configuration of a Single Receive Object for Data Frames
      4. 25.10.4 Configuration of a Single Receive Object for Remote Frames
      5. 25.10.5 Configuration of a FIFO Buffer
    11. 25.11 Message Handling
      1. 25.11.1  Message Handler Overview
      2. 25.11.2  Receive/Transmit Priority
      3. 25.11.3  Transmission of Messages in Event Driven CAN Communication
      4. 25.11.4  Updating a Transmit Object
      5. 25.11.5  Changing a Transmit Object
      6. 25.11.6  Acceptance Filtering of Received Messages
      7. 25.11.7  Reception of Data Frames
      8. 25.11.8  Reception of Remote Frames
      9. 25.11.9  Reading Received Messages
      10. 25.11.10 Requesting New Data for a Receive Object
      11. 25.11.11 Storing Received Messages in FIFO Buffers
      12. 25.11.12 Reading from a FIFO Buffer
    12. 25.12 CAN Bit Timing
      1. 25.12.1 Bit Time and Bit Rate
        1. 25.12.1.1 Synchronization Segment
        2. 25.12.1.2 Propagation Time Segment
        3. 25.12.1.3 Phase Buffer Segments and Synchronization
        4. 25.12.1.4 Oscillator Tolerance Range
      2. 25.12.2 Configuration of the CAN Bit Timing
        1. 25.12.2.1 Calculation of the Bit Timing Parameters
        2. 25.12.2.2 Example for Bit Timing at High Baudrate
        3. 25.12.2.3 Example for Bit Timing at Low Baudrate
    13. 25.13 Message Interface Register Sets
      1. 25.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 25.13.2 Message Interface Register Set 3 (IF3)
    14. 25.14 Message RAM
      1. 25.14.1 Structure of Message Objects
      2. 25.14.2 Addressing Message Objects in RAM
      3. 25.14.3 Message RAM Representation in Debug Mode
    15. 25.15 Software
      1. 25.15.1 CAN Examples
        1. 25.15.1.1  CAN Dual Core Example - C28X_DUAL
        2. 25.15.1.2  CAN External Loopback
        3. 25.15.1.3  CAN External Loopback - C28X_DUAL
        4. 25.15.1.4  CAN External Loopback with Interrupts
        5. 25.15.1.5  CAN External Loopback with Interrupts - C28X_DUAL
        6. 25.15.1.6  CAN External Loopback with DMA
        7. 25.15.1.7  CAN Transmit and Receive Configurations
        8. 25.15.1.8  CAN Error Generation Example
        9. 25.15.1.9  CAN Remote Request Loopback
        10. 25.15.1.10 CAN example that illustrates the usage of Mask registers
    16. 25.16 CAN Registers
      1. 25.16.1 CAN Base Address Table
      2. 25.16.2 CAN_REGS Registers
      3. 25.16.3 CAN Registers to Driverlib Functions
  28. 26EtherCAT® SubordinateDevice Controller (ESC)
    1. 26.1 Introduction
      1. 26.1.1  ECAT Related Collateral
      2. 26.1.2  ESC Features
      3. 26.1.3  ESC Subsystem Integrated Features
      4. 26.1.4  F28P65x ESC versus Beckhoff ET1100
      5. 26.1.5  EtherCAT IP Block Diagram
      6. 26.1.6  ESC Functional Blocks
        1. 26.1.6.1  Interface to EtherCAT MainDevice
        2. 26.1.6.2  Process Data Interface
        3. 26.1.6.3  General-Purpose Inputs and Outputs
        4. 26.1.6.4  EtherCAT Processing Unit (EPU)
        5. 26.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 26.1.6.6  Sync Manager
        7. 26.1.6.7  Monitoring
        8. 26.1.6.8  Reset Controller
        9. 26.1.6.9  PHY Management
        10. 26.1.6.10 Distributed Clock (DC)
        11. 26.1.6.11 EEPROM
        12. 26.1.6.12 Status / LEDs
      7. 26.1.7  EtherCAT Physical Layer
        1. 26.1.7.1 MII Interface
        2. 26.1.7.2 PHY Management Interface
          1. 26.1.7.2.1 PHY Address Configuration
          2. 26.1.7.2.2 PHY Reset Signal
          3. 26.1.7.2.3 PHY Clock
      8. 26.1.8  EtherCAT Protocol
      9. 26.1.9  EtherCAT State Machine (ESM)
      10. 26.1.10 More Information on EtherCAT
      11. 26.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 26.2 ESC and ESCSS Description
      1. 26.2.1  ESC RAM Parity and Memory Address Maps
        1. 26.2.1.1 ESC RAM Parity Logic
        2. 26.2.1.2 CPU1 and CPU2 ESC Memory Address Map
      2. 26.2.2  Local Host Communication
        1. 26.2.2.1 Byte Accessibility Through PDI
        2. 26.2.2.2 Software Details for Operation Across Clock Domains
      3. 26.2.3  Debug Emulation Mode Operation
      4. 26.2.4  ESC SubSystem
        1. 26.2.4.1 CPU1 Bus Interface
        2. 26.2.4.2 CPU2 Bus Interface
      5. 26.2.5  Interrupts and Interrupt Mapping
      6. 26.2.6  Power, Clocks, and Resets
        1. 26.2.6.1 Power
        2. 26.2.6.2 Clocking
        3. 26.2.6.3 Resets
          1. 26.2.6.3.1 Chip-Level Reset
          2. 26.2.6.3.2 EtherCAT Soft Resets
          3. 26.2.6.3.3 Reset Out (RESET_OUT)
      7. 26.2.7  LED Controls
      8. 26.2.8  SubordinateDevice Node Configuration and EEPROM
      9. 26.2.9  General-Purpose Inputs and Outputs
        1. 26.2.9.1 General-Purpose Inputs
        2. 26.2.9.2 General-Purpose Output
      10. 26.2.10 Distributed Clocks – Sync and Latch
        1. 26.2.10.1 Clock Synchronization
        2. 26.2.10.2 SYNC Signals
          1. 26.2.10.2.1 Seeking Host Intervention
        3. 26.2.10.3 LATCH Signals
          1. 26.2.10.3.1 Timestamping
        4. 26.2.10.4 Device Control and Synchronization
          1. 26.2.10.4.1 Synchronization of PWM
          2. 26.2.10.4.2 ECAP SYNC Inputs
          3. 26.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 26.3 Software Initialization Sequence and Allocating Ownership
    4. 26.4 ESC Configuration Constants
    5. 26.5 EtherCAT IP Registers
      1. 26.5.1 ETHERCAT Base Address Table
      2. 26.5.2 ESCSS_REGS Registers
      3. 26.5.3 ESCSS_CONFIG_REGS Registers
      4. 26.5.4 ESC_SS Registers to Driverlib Functions
  29. 27Fast Serial Interface (FSI)
    1. 27.1 Introduction
      1. 27.1.1 FSI Related Collateral
      2. 27.1.2 FSI Features
    2. 27.2 System-level Integration
      1. 27.2.1 CPU Interface
      2. 27.2.2 Signal Description
        1. 27.2.2.1 Configuring Device Pins
      3. 27.2.3 FSI Interrupts
        1. 27.2.3.1 Transmitter Interrupts
        2. 27.2.3.2 Receiver Interrupts
        3. 27.2.3.3 Configuring Interrupts
        4. 27.2.3.4 Handling Interrupts
      4. 27.2.4 CLA Task Triggering
      5. 27.2.5 DMA Interface
      6. 27.2.6 External Frame Trigger Mux
    3. 27.3 FSI Functional Description
      1. 27.3.1  Introduction to Operation
      2. 27.3.2  FSI Transmitter Module
        1. 27.3.2.1 Initialization
        2. 27.3.2.2 FSI_TX Clocking
        3. 27.3.2.3 Transmitting Frames
          1. 27.3.2.3.1 Software Triggered Frames
          2. 27.3.2.3.2 Externally Triggered Frames
          3. 27.3.2.3.3 Ping Frame Generation
            1. 27.3.2.3.3.1 Automatic Ping Frames
            2. 27.3.2.3.3.2 Software Triggered Ping Frame
            3. 27.3.2.3.3.3 Externally Triggered Ping Frame
          4. 27.3.2.3.4 Transmitting Frames with DMA
        4. 27.3.2.4 Transmit Buffer Management
        5. 27.3.2.5 CRC Submodule
        6. 27.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 27.3.2.7 Reset
      3. 27.3.3  FSI Receiver Module
        1. 27.3.3.1  Initialization
        2. 27.3.3.2  FSI_RX Clocking
        3. 27.3.3.3  Receiving Frames
          1. 27.3.3.3.1 Receiving Frames with DMA
        4. 27.3.3.4  Ping Frame Watchdog
        5. 27.3.3.5  Frame Watchdog
        6. 27.3.3.6  Delay Line Control
        7. 27.3.3.7  Buffer Management
        8. 27.3.3.8  CRC Submodule
        9. 27.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 27.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 27.3.3.11 FSI_RX Reset
      4. 27.3.4  Frame Format
        1. 27.3.4.1 FSI Frame Phases
        2. 27.3.4.2 Frame Types
          1. 27.3.4.2.1 Ping Frames
          2. 27.3.4.2.2 Error Frames
          3. 27.3.4.2.3 Data Frames
        3. 27.3.4.3 Multi-Lane Transmission
      5. 27.3.5  Flush Sequence
      6. 27.3.6  Internal Loopback
      7. 27.3.7  CRC Generation
      8. 27.3.8  ECC Module
      9. 27.3.9  Tag Matching
      10. 27.3.10 User Data Filtering (UDATA Matching)
      11. 27.3.11 TDM Configurations
      12. 27.3.12 FSI Trigger Generation
      13. 27.3.13 FSI-SPI Compatibility Mode
        1. 27.3.13.1 Available SPI Modes
          1. 27.3.13.1.1 FSITX as SPI Controller, Transmit Only
            1. 27.3.13.1.1.1 Initialization
            2. 27.3.13.1.1.2 Operation
          2. 27.3.13.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 27.3.13.1.2.1 Initialization
            2. 27.3.13.1.2.2 Operation
          3. 27.3.13.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 27.3.13.1.3.1 Initialization
            2. 27.3.13.1.3.2 Operation
    4. 27.4 FSI Programing Guide
      1. 27.4.1 Establishing the Communication Link
        1. 27.4.1.1 Establishing the Communication Link from the Main Device
        2. 27.4.1.2 Establishing the Communication Link from the Remote Device
      2. 27.4.2 Register Protection
      3. 27.4.3 Emulation Mode
    5. 27.5 Software
      1. 27.5.1 FSI Examples
        1. 27.5.1.1 FSI Loopback:CPU Control - SINGLE_CORE
        2. 27.5.1.2 FSI data transfers upon CPU Timer event - SINGLE_CORE
    6. 27.6 FSI Registers
      1. 27.6.1 FSI Base Address Table
      2. 27.6.2 FSI_TX_REGS Registers
      3. 27.6.3 FSI_RX_REGS Registers
      4. 27.6.4 FSI Registers to Driverlib Functions
  30. 28Inter-Integrated Circuit Module (I2C)
    1. 28.1 Introduction
      1. 28.1.1 I2C Related Collateral
      2. 28.1.2 Features
      3. 28.1.3 Features Not Supported
      4. 28.1.4 Functional Overview
      5. 28.1.5 Clock Generation
      6. 28.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 28.1.6.1 Formula for the Controller Clock Period
    2. 28.2 Configuring Device Pins
    3. 28.3 I2C Module Operational Details
      1. 28.3.1  Input and Output Voltage Levels
      2. 28.3.2  Selecting Pullup Resistors
      3. 28.3.3  Data Validity
      4. 28.3.4  Operating Modes
      5. 28.3.5  I2C Module START and STOP Conditions
      6. 28.3.6  Non-repeat Mode versus Repeat Mode
      7. 28.3.7  Serial Data Formats
        1. 28.3.7.1 7-Bit Addressing Format
        2. 28.3.7.2 10-Bit Addressing Format
        3. 28.3.7.3 Free Data Format
        4. 28.3.7.4 Using a Repeated START Condition
      8. 28.3.8  Clock Synchronization
      9. 28.3.9  Arbitration
      10. 28.3.10 Digital Loopback Mode
      11. 28.3.11 NACK Bit Generation
    4. 28.4 Interrupt Requests Generated by the I2C Module
      1. 28.4.1 Basic I2C Interrupt Requests
      2. 28.4.2 I2C FIFO Interrupts
    5. 28.5 Resetting or Disabling the I2C Module
    6. 28.6 Software
      1. 28.6.1 I2C Examples
        1. 28.6.1.1 I2C Digital Loopback with FIFO Interrupts - SINGLE_CORE
        2. 28.6.1.2 I2C EEPROM - SINGLE_CORE
        3. 28.6.1.3 I2C Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        4. 28.6.1.4 I2C Extended Clock Stretching Controller TX - SINGLE_CORE
        5. 28.6.1.5 I2C Extended Clock Stretching Target RX - SINGLE_CORE
    7. 28.7 I2C Registers
      1. 28.7.1 I2C Base Address Table
      2. 28.7.2 I2C_REGS Registers
      3. 28.7.3 I2C Registers to Driverlib Functions
  31. 29Power Management Bus Module (PMBus)
    1. 29.1 Introduction
      1. 29.1.1 PMBUS Related Collateral
      2. 29.1.2 Features
      3. 29.1.3 Block Diagram
    2. 29.2 Configuring Device Pins
    3. 29.3 Target Mode Operation
      1. 29.3.1 Configuration
      2. 29.3.2 Message Handling
        1. 29.3.2.1  Quick Command
        2. 29.3.2.2  Send Byte
        3. 29.3.2.3  Receive Byte
        4. 29.3.2.4  Write Byte and Write Word
        5. 29.3.2.5  Read Byte and Read Word
        6. 29.3.2.6  Process Call
        7. 29.3.2.7  Block Write
        8. 29.3.2.8  Block Read
        9. 29.3.2.9  Block Write-Block Read Process Call
        10. 29.3.2.10 Alert Response
        11. 29.3.2.11 Extended Command
        12. 29.3.2.12 Group Command
    4. 29.4 Controller Mode Operation
      1. 29.4.1 Configuration
      2. 29.4.2 Message Handling
        1. 29.4.2.1  Quick Command
        2. 29.4.2.2  Send Byte
        3. 29.4.2.3  Receive Byte
        4. 29.4.2.4  Write Byte and Write Word
        5. 29.4.2.5  Read Byte and Read Word
        6. 29.4.2.6  Process Call
        7. 29.4.2.7  Block Write
        8. 29.4.2.8  Block Read
        9. 29.4.2.9  Block Write-Block Read Process Call
        10. 29.4.2.10 Alert Response
        11. 29.4.2.11 Extended Command
        12. 29.4.2.12 Group Command
    5. 29.5 PMBUS Registers
      1. 29.5.1 PMBUS Base Address Table
      2. 29.5.2 PMBUS_REGS Registers
      3. 29.5.3 PMBUS Registers to Driverlib Functions
  32. 30Serial Communications Interface (SCI)
    1. 30.1  Introduction
      1. 30.1.1 Features
      2. 30.1.2 SCI Related Collateral
      3. 30.1.3 Block Diagram
    2. 30.2  Architecture
    3. 30.3  SCI Module Signal Summary
    4. 30.4  Configuring Device Pins
    5. 30.5  Multiprocessor and Asynchronous Communication Modes
    6. 30.6  SCI Programmable Data Format
    7. 30.7  SCI Multiprocessor Communication
      1. 30.7.1 Recognizing the Address Byte
      2. 30.7.2 Controlling the SCI TX and RX Features
      3. 30.7.3 Receipt Sequence
    8. 30.8  Idle-Line Multiprocessor Mode
      1. 30.8.1 Idle-Line Mode Steps
      2. 30.8.2 Block Start Signal
      3. 30.8.3 Wake-Up Temporary (WUT) Flag
        1. 30.8.3.1 Sending a Block Start Signal
      4. 30.8.4 Receiver Operation
    9. 30.9  Address-Bit Multiprocessor Mode
      1. 30.9.1 Sending an Address
    10. 30.10 SCI Communication Format
      1. 30.10.1 Receiver Signals in Communication Modes
      2. 30.10.2 Transmitter Signals in Communication Modes
    11. 30.11 SCI Port Interrupts
      1. 30.11.1 Break Detect
    12. 30.12 SCI Baud Rate Calculations
    13. 30.13 SCI Enhanced Features
      1. 30.13.1 SCI FIFO Description
      2. 30.13.2 SCI Auto-Baud
      3. 30.13.3 Autobaud-Detect Sequence
    14. 30.14 Software
      1. 30.14.1 SCI Examples
        1. 30.14.1.1 Tune Baud Rate via UART Example
        2. 30.14.1.2 SCI FIFO Digital Loop Back
        3. 30.14.1.3 SCI Digital Loop Back with Interrupts
        4. 30.14.1.4 SCI Echoback
        5. 30.14.1.5 stdout redirect example
    15. 30.15 SCI Registers
      1. 30.15.1 SCI Base Address Table
      2. 30.15.2 SCI_REGS Registers
      3. 30.15.3 SCI Registers to Driverlib Functions
  33. 31Serial Peripheral Interface (SPI)
    1. 31.1 Introduction
      1. 31.1.1 Features
      2. 31.1.2 SPI Related Collateral
      3. 31.1.3 Block Diagram
    2. 31.2 System-Level Integration
      1. 31.2.1 SPI Module Signals
      2. 31.2.2 Configuring Device Pins
        1. 31.2.2.1 GPIOs Required for High-Speed Mode
      3. 31.2.3 SPI Interrupts
      4. 31.2.4 DMA Support
    3. 31.3 SPI Operation
      1. 31.3.1  Introduction to Operation
      2. 31.3.2  Controller Mode
      3. 31.3.3  Peripheral Mode
      4. 31.3.4  Data Format
        1. 31.3.4.1 Transmission of Bit from SPIRXBUF
      5. 31.3.5  Baud Rate Selection
        1. 31.3.5.1 Baud Rate Determination
        2. 31.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 31.3.6  SPI Clocking Schemes
      7. 31.3.7  SPI FIFO Description
      8. 31.3.8  SPI DMA Transfers
        1. 31.3.8.1 Transmitting Data Using SPI with DMA
        2. 31.3.8.2 Receiving Data Using SPI with DMA
      9. 31.3.9  SPI High-Speed Mode
      10. 31.3.10 SPI 3-Wire Mode Description
    4. 31.4 Programming Procedure
      1. 31.4.1 Initialization Upon Reset
      2. 31.4.2 Configuring the SPI
      3. 31.4.3 Configuring the SPI for High-Speed Mode
      4. 31.4.4 Data Transfer Example
      5. 31.4.5 SPI 3-Wire Mode Code Examples
        1. 31.4.5.1 3-Wire Controller Mode Transmit
        2.       1721
          1. 31.4.5.2.1 3-Wire Controller Mode Receive
        3.       1723
          1. 31.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1725
          1. 31.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 31.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 31.5 Software
      1. 31.5.1 SPI Examples
        1. 31.5.1.1 SPI Digital Loopback - SINGLE_CORE
        2. 31.5.1.2 SPI Digital Loopback with FIFO Interrupts - SINGLE_CORE
        3. 31.5.1.3 SPI Digital External Loopback without FIFO Interrupts - SINGLE_CORE
        4. 31.5.1.4 SPI Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        5. 31.5.1.5 SPI Digital Loopback with DMA - SINGLE_CORE
    6. 31.6 SPI Registers
      1. 31.6.1 SPI Base Address Table
      2. 31.6.2 SPI_REGS Registers
      3. 31.6.3 SPI Registers to Driverlib Functions
  34. 32Universal Serial Bus (USB) Controller
    1. 32.1 Introduction
      1. 32.1.1 Features
      2. 32.1.2 USB Related Collateral
      3. 32.1.3 Block Diagram
        1. 32.1.3.1 Signal Description
        2. 32.1.3.2 VBus Recommendations
    2. 32.2 Functional Description
      1. 32.2.1 Operation as a Device
        1. 32.2.1.1 Control and Configurable Endpoints
          1. 32.2.1.1.1 IN Transactions as a Device
          2. 32.2.1.1.2 Out Transactions as a Device
          3. 32.2.1.1.3 Scheduling
          4. 32.2.1.1.4 Additional Actions
          5. 32.2.1.1.5 Device Mode Suspend
          6. 32.2.1.1.6 Start of Frame
          7. 32.2.1.1.7 USB Reset
          8. 32.2.1.1.8 Connect/Disconnect
      2. 32.2.2 Operation as a Host
        1. 32.2.2.1 Endpoint Registers
        2. 32.2.2.2 IN Transactions as a Host
        3. 32.2.2.3 OUT Transactions as a Host
        4. 32.2.2.4 Transaction Scheduling
        5. 32.2.2.5 USB Hubs
        6. 32.2.2.6 Babble
        7. 32.2.2.7 Host SUSPEND
        8. 32.2.2.8 USB RESET
        9. 32.2.2.9 Connect/Disconnect
      3. 32.2.3 DMA Operation
      4. 32.2.4 Address/Data Bus Bridge
    3. 32.3 Initialization and Configuration
      1. 32.3.1 Pin Configuration
      2. 32.3.2 Endpoint Configuration
    4. 32.4 USB Global Interrupts
    5. 32.5 Software
      1. 32.5.1 USB Examples
        1. 32.5.1.1  USB CDC serial example
        2. 32.5.1.2  USB HID Mouse Device
        3. 32.5.1.3  USB Device Keyboard
        4. 32.5.1.4  USB Generic Bulk Device
        5. 32.5.1.5  USB HID Mouse Host
        6. 32.5.1.6  USB HID Keyboard Host
        7. 32.5.1.7  USB Mass Storage Class Host
        8. 32.5.1.8  USB Dual Detect
        9. 32.5.1.9  USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk)
        10. 32.5.1.10 USB HUB Host example
    6. 32.6 USB Registers
      1. 32.6.1 USB Base Address Table
      2. 32.6.2 USB_REGS Registers
      3. 32.6.3 USB Registers to Driverlib Functions
  35. 33Advanced Encryption Standard (AES) Accelerator
    1. 33.1 Introduction
      1. 33.1.1 AES Block Diagram
        1. 33.1.1.1 Interfaces
        2. 33.1.1.2 AES Subsystem
        3. 33.1.1.3 AES Wide-Bus Engine
      2. 33.1.2 AES Algorithm
    2. 33.2 AES Operating Modes
      1. 33.2.1  GCM Operation
      2. 33.2.2  CCM Operation
      3. 33.2.3  XTS Operation
      4. 33.2.4  ECB Feedback Mode
      5. 33.2.5  CBC Feedback Mode
      6. 33.2.6  CTR and ICM Feedback Modes
      7. 33.2.7  CFB Mode
      8. 33.2.8  F8 Mode
      9. 33.2.9  F9 Operation
      10. 33.2.10 CBC-MAC Operation
    3. 33.3 Extended and Combined Modes of Operations
      1. 33.3.1 GCM Protocol Operation
      2. 33.3.2 CCM Protocol Operation
      3. 33.3.3 Hardware Requests
    4. 33.4 AES Module Programming Guide
      1. 33.4.1 AES Low-Level Programming Models
        1. 33.4.1.1 Global Initialization
        2. 33.4.1.2 AES Operating Modes Configuration
        3. 33.4.1.3 AES Mode Configurations
        4. 33.4.1.4 AES Events Servicing
    5. 33.5 Software
      1. 33.5.1 AES Examples
        1. 33.5.1.1 AES ECB Encryption Example
        2. 33.5.1.2 AES ECB De-cryption Example
        3. 33.5.1.3 AES GCM Encryption Example
        4. 33.5.1.4 AES GCM Decryption Example
    6. 33.6 AES Registers
      1. 33.6.1 AES Base Address Table
      2. 33.6.2 AES_REGS Registers
      3. 33.6.3 AES_SS_REGS Registers
      4. 33.6.4 Register to Driverlib Function Mapping
        1. 33.6.4.1 AES Registers to Driverlib Functions
        2. 33.6.4.2 AES_SS Registers to Driverlib Functions
  36. 34Embedded Pattern Generator (EPG)
    1. 34.1 Introduction
      1. 34.1.1 Features
      2. 34.1.2 EPG Block Diagram
      3. 34.1.3 EPG Related Collateral
    2. 34.2 Clock Generator Modules
      1. 34.2.1 DCLK (50% duty cycle clock)
      2. 34.2.2 Clock Stop
    3. 34.3 Signal Generator Module
    4. 34.4 EPG Peripheral Signal Mux Selection
    5. 34.5 Application Software Notes
    6. 34.6 EPG Example Use Cases
      1. 34.6.1 EPG Example: Synchronous Clocks with Offset
        1. 34.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 34.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 34.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 34.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 34.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
      4. 34.6.4 EPG Example: Clock and Data Pair
        1. 34.6.4.1 Clock and Data Pair Register Configuration
      5. 34.6.5 EPG Example: Clock and Skewed Data Pair
        1. 34.6.5.1 Clock and Skewed Data Pair Register Configuration
      6. 34.6.6 EPG Example: Capturing Serial Data with a Known Baud Rate
        1. 34.6.6.1 Capturing Serial Data with a Known Baud Rate Register Configuration
    7. 34.7 EPG Interrupt
    8. 34.8 Software
      1. 34.8.1 EPG Examples
        1. 34.8.1.1 EPG Generating Synchronous Clocks - SINGLE_CORE
        2. 34.8.1.2 EPG Generating Two Offset Clocks - SINGLE_CORE
        3. 34.8.1.3 EPG Generating Two Offset Clocks With SIGGEN - SINGLE_CORE
        4. 34.8.1.4 EPG Generate Serial Data - SINGLE_CORE
        5. 34.8.1.5 EPG Generate Serial Data Shift Mode - SINGLE_CORE
    9. 34.9 EPG Registers
      1. 34.9.1 EPG Base Address Table
      2. 34.9.2 EPG_REGS Registers
      3. 34.9.3 EPG_MUX_REGS Registers
      4. 34.9.4 EPG Registers to Driverlib Functions
  37. 35Modular Controller Area Network (MCAN)
    1. 35.1 MCAN Introduction
      1. 35.1.1 MCAN Related Collateral
      2. 35.1.2 MCAN Features
    2. 35.2 MCAN Environment
    3. 35.3 CAN Network Basics
    4. 35.4 MCAN Integration
    5. 35.5 MCAN Functional Description
      1. 35.5.1  Module Clocking Requirements
      2. 35.5.2  Interrupt Requests
      3. 35.5.3  Operating Modes
        1. 35.5.3.1 Software Initialization
        2. 35.5.3.2 Normal Operation
        3. 35.5.3.3 CAN FD Operation
      4. 35.5.4  Transmitter Delay Compensation
        1. 35.5.4.1 Description
        2. 35.5.4.2 Transmitter Delay Compensation Measurement
      5. 35.5.5  Restricted Operation Mode
      6. 35.5.6  Bus Monitoring Mode
      7. 35.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 35.5.7.1 Frame Transmission in DAR Mode
      8. 35.5.8  Clock Stop Mode
        1. 35.5.8.1 Suspend Mode
        2. 35.5.8.2 Wakeup Request
      9. 35.5.9  Test Modes
        1. 35.5.9.1 External Loop Back Mode
        2. 35.5.9.2 Internal Loop Back Mode
      10. 35.5.10 Timestamp Generation
        1. 35.5.10.1 External Timestamp Counter
      11. 35.5.11 Timeout Counter
      12. 35.5.12 Safety
        1. 35.5.12.1 ECC Wrapper
        2. 35.5.12.2 ECC Aggregator
          1. 35.5.12.2.1 ECC Aggregator Overview
          2. 35.5.12.2.2 ECC Aggregator Registers
        3. 35.5.12.3 Reads to ECC Control and Status Registers
        4. 35.5.12.4 ECC Interrupts
      13. 35.5.13 Rx Handling
        1. 35.5.13.1 Acceptance Filtering
          1. 35.5.13.1.1 Range Filter
          2. 35.5.13.1.2 Filter for Specific IDs
          3. 35.5.13.1.3 Classic Bit Mask Filter
          4. 35.5.13.1.4 Standard Message ID Filtering
          5. 35.5.13.1.5 Extended Message ID Filtering
        2. 35.5.13.2 Rx FIFOs
          1. 35.5.13.2.1 Rx FIFO Blocking Mode
          2. 35.5.13.2.2 Rx FIFO Overwrite Mode
        3. 35.5.13.3 Dedicated Rx Buffers
          1. 35.5.13.3.1 Rx Buffer Handling
      14. 35.5.14 Tx Handling
        1. 35.5.14.1 Transmit Pause
        2. 35.5.14.2 Dedicated Tx Buffers
        3. 35.5.14.3 Tx FIFO
        4. 35.5.14.4 Tx Queue
        5. 35.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 35.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 35.5.14.7 Transmit Cancellation
        8. 35.5.14.8 Tx Event Handling
      15. 35.5.15 FIFO Acknowledge Handling
      16. 35.5.16 Message RAM
        1. 35.5.16.1 Message RAM Configuration
        2. 35.5.16.2 Rx Buffer and FIFO Element
        3. 35.5.16.3 Tx Buffer Element
        4. 35.5.16.4 Tx Event FIFO Element
        5. 35.5.16.5 Standard Message ID Filter Element
        6. 35.5.16.6 Extended Message ID Filter Element
    6. 35.6 Software
      1. 35.6.1 MCAN Examples
        1. 35.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        2. 35.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
    7. 35.7 MCAN Registers
      1. 35.7.1 MCAN Base Address Table
      2. 35.7.2 MCANSS_REGS Registers
      3. 35.7.3 MCAN_REGS Registers
      4. 35.7.4 MCAN_ERROR_REGS Registers
      5. 35.7.5 MCAN Registers to Driverlib Functions
  38. 36Universal Asynchronous Receiver/Transmitter (UART)
    1. 36.1 Introduction
      1. 36.1.1 Features
      2. 36.1.2 Block Diagram
    2. 36.2 Functional Description
      1. 36.2.1 Transmit and Receive Logic
      2. 36.2.2 Baud-Rate Generation
      3. 36.2.3 Data Transmission
      4. 36.2.4 Serial IR (SIR)
      5. 36.2.5 9-Bit UART Mode
      6. 36.2.6 FIFO Operation
      7. 36.2.7 Interrupts
      8. 36.2.8 Loopback Operation
      9. 36.2.9 DMA Operation
        1. 36.2.9.1 Receiving Data Using UART with DMA
        2. 36.2.9.2 Transmitting Data Using UART with DMA
    3. 36.3 Initialization and Configuration
    4. 36.4 Software
      1. 36.4.1 UART Examples
        1. 36.4.1.1 UART Loopback - SINGLE_CORE
        2. 36.4.1.2 UART Loopback with Interrupt - SINGLE_CORE
        3. 36.4.1.3 UART Loopback with DMA - SINGLE_CORE
    5. 36.5 UART Registers
      1. 36.5.1 UART Base Address Table
      2. 36.5.2 UART_REGS Registers
      3. 36.5.3 UART_REGS_WRITE Registers
      4. 36.5.4 UART Registers to Driverlib Functions
  39. 37Local Interconnect Network (LIN)
    1. 37.1 LIN Overview
      1. 37.1.1 SCI Features
      2. 37.1.2 LIN Features
      3. 37.1.3 LIN Related Collateral
      4. 37.1.4 Block Diagram
    2. 37.2 Serial Communications Interface Module
      1. 37.2.1 SCI Communication Formats
        1. 37.2.1.1 SCI Frame Formats
        2. 37.2.1.2 SCI Asynchronous Timing Mode
        3. 37.2.1.3 SCI Baud Rate
          1. 37.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 37.2.1.4 SCI Multiprocessor Communication Modes
          1. 37.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 37.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 37.2.1.5 SCI Multibuffered Mode
      2. 37.2.2 SCI Interrupts
        1. 37.2.2.1 Transmit Interrupt
        2. 37.2.2.2 Receive Interrupt
        3. 37.2.2.3 WakeUp Interrupt
        4. 37.2.2.4 Error Interrupts
      3. 37.2.3 SCI DMA Interface
        1. 37.2.3.1 Receive DMA Requests
        2. 37.2.3.2 Transmit DMA Requests
      4. 37.2.4 SCI Configurations
        1. 37.2.4.1 Receiving Data
          1. 37.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 37.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 37.2.4.2 Transmitting Data
          1. 37.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 37.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 37.2.5 SCI Low-Power Mode
        1. 37.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 37.3 Local Interconnect Network Module
      1. 37.3.1 LIN Communication Formats
        1. 37.3.1.1  LIN Standards
        2. 37.3.1.2  Message Frame
          1. 37.3.1.2.1 Message Header
          2. 37.3.1.2.2 Response
        3. 37.3.1.3  Synchronizer
        4. 37.3.1.4  Baud Rate
          1. 37.3.1.4.1 Fractional Divider
          2. 37.3.1.4.2 Superfractional Divider
            1. 37.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 37.3.1.5  Header Generation
          1. 37.3.1.5.1 Event Triggered Frame Handling
          2. 37.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 37.3.1.6  Extended Frames Handling
        7. 37.3.1.7  Timeout Control
          1. 37.3.1.7.1 No-Response Error (NRE)
          2. 37.3.1.7.2 Bus Idle Detection
          3. 37.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 37.3.1.8  TXRX Error Detector (TED)
          1. 37.3.1.8.1 Bit Errors
          2. 37.3.1.8.2 Physical Bus Errors
          3. 37.3.1.8.3 ID Parity Errors
          4. 37.3.1.8.4 Checksum Errors
        9. 37.3.1.9  Message Filtering and Validation
        10. 37.3.1.10 Receive Buffers
        11. 37.3.1.11 Transmit Buffers
      2. 37.3.2 LIN Interrupts
      3. 37.3.3 Servicing LIN Interrupts
      4. 37.3.4 LIN DMA Interface
        1. 37.3.4.1 LIN Receive DMA Requests
        2. 37.3.4.2 LIN Transmit DMA Requests
      5. 37.3.5 LIN Configurations
        1. 37.3.5.1 Receiving Data
          1. 37.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 37.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 37.3.5.2 Transmitting Data
          1. 37.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 37.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 37.4 Low-Power Mode
      1. 37.4.1 Entering Sleep Mode
      2. 37.4.2 Wakeup
      3. 37.4.3 Wakeup Timeouts
    5. 37.5 Emulation Mode
    6. 37.6 Software
      1. 37.6.1 LIN Examples
        1. 37.6.1.1 LIN Internal Loopback with Interrupts - SINGLE_CORE
        2. 37.6.1.2 LIN SCI Mode Internal Loopback with Interrupts - SINGLE_CORE
        3. 37.6.1.3 LIN SCI MODE Internal Loopback with DMA - SINGLE_CORE
        4. 37.6.1.4 LIN Internal Loopback without interrupts (polled mode) - SINGLE_CORE
        5. 37.6.1.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA - SINGLE_CORE
    7. 37.7 SCI/LIN Registers
      1. 37.7.1 LIN Base Address Table
      2. 37.7.2 LIN_REGS Registers
      3. 37.7.3 LIN Registers to Driverlib Functions
  40. 38Lockstep Compare Module (LCM)
    1. 38.1 Introduction
      1. 38.1.1 Features
      2. 38.1.2 Block Diagram
    2. 38.2 Enabling LCM Comparators
    3. 38.3 Disabling LCM Redundant Module
    4. 38.4 LCM Error Handling
    5. 38.5 LCM Error Flags
    6. 38.6 Debug Mode with LCM
    7. 38.7 Register Parity Error Protection
    8. 38.8 Functional Logic
      1. 38.8.1 Comparator Logic
      2. 38.8.2 Self-Test Logic
        1. 38.8.2.1 Match Test Mode
        2. 38.8.2.2 Mismatch Test Mode
      3. 38.8.3 Error Injection Tests
        1. 38.8.3.1 Comparator Error Force Test
        2. 38.8.3.2 Register Parity Error Test
    9. 38.9 LCM Registers
      1. 38.9.1 LCM Base Address Table
      2. 38.9.2 LCM_REGS Registers
      3. 38.9.3 LCM Registers to Driverlib Functions
  41. 39Revision History

35.7.3 MCAN_REGS Registers

Table 35-30 lists the memory-mapped registers for the MCAN_REGS registers. All register offset addresses not listed in Table 35-30 should be considered as reserved locations and the register contents should not be modified.

Table 35-30 MCAN_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hMCAN_CRELMCAN Core Release RegisterGo
2hMCAN_ENDNMCAN Endian RegisterGo
6hMCAN_DBTPMCAN Data Bit Timing and Prescaler RegisterGo
8hMCAN_TESTMCAN Test RegisterGo
AhMCAN_RWDMCAN RAM WatchdogGo
ChMCAN_CCCRMCAN CC Control RegisterGo
EhMCAN_NBTPMCAN Nominal Bit Timing and Prescaler RegisterGo
10hMCAN_TSCCMCAN Timestamp Counter ConfigurationGo
12hMCAN_TSCVMCAN Timestamp Counter ValueGo
14hMCAN_TOCCMCAN Timeout Counter ConfigurationGo
16hMCAN_TOCVMCAN Timeout Counter ValueGo
20hMCAN_ECRMCAN Error Counter RegisterGo
22hMCAN_PSRMCAN Protocol Status RegisterGo
24hMCAN_TDCRMCAN Transmitter Delay Compensation RegisterGo
28hMCAN_IRMCAN Interrupt RegisterGo
2AhMCAN_IEMCAN Interrupt EnableGo
2ChMCAN_ILSMCAN Interrupt Line SelectGo
2EhMCAN_ILEMCAN Interrupt Line EnableGo
40hMCAN_GFCMCAN Global Filter ConfigurationGo
42hMCAN_SIDFCMCAN Standard ID Filter ConfigurationGo
44hMCAN_XIDFCMCAN Extended ID Filter ConfigurationGo
48hMCAN_XIDAMMCAN Extended ID and MaskGo
4AhMCAN_HPMSMCAN High Priority Message StatusGo
4ChMCAN_NDAT1MCAN New Data 1Go
4EhMCAN_NDAT2MCAN New Data 2Go
50hMCAN_RXF0CMCAN Rx FIFO 0 ConfigurationGo
52hMCAN_RXF0SMCAN Rx FIFO 0 StatusGo
54hMCAN_RXF0AMCAN Rx FIFO 0 AcknowledgeGo
56hMCAN_RXBCMCAN Rx Buffer ConfigurationGo
58hMCAN_RXF1CMCAN Rx FIFO 1 ConfigurationGo
5AhMCAN_RXF1SMCAN Rx FIFO 1 StatusGo
5ChMCAN_RXF1AMCAN Rx FIFO 1 AcknowledgeGo
5EhMCAN_RXESCMCAN Rx Buffer / FIFO Element Size ConfigurationGo
60hMCAN_TXBCMCAN Tx Buffer ConfigurationGo
62hMCAN_TXFQSMCAN Tx FIFO / Queue StatusGo
64hMCAN_TXESCMCAN Tx Buffer Element Size ConfigurationGo
66hMCAN_TXBRPMCAN Tx Buffer Request PendingGo
68hMCAN_TXBARMCAN Tx Buffer Add RequestGo
6AhMCAN_TXBCRMCAN Tx Buffer Cancellation RequestGo
6ChMCAN_TXBTOMCAN Tx Buffer Transmission OccurredGo
6EhMCAN_TXBCFMCAN Tx Buffer Cancellation FinishedGo
70hMCAN_TXBTIEMCAN Tx Buffer Transmission Interrupt EnableGo
72hMCAN_TXBCIEMCAN Tx Buffer Cancellation Finished Interrupt EnableGo
78hMCAN_TXEFCMCAN Tx Event FIFO ConfigurationGo
7AhMCAN_TXEFSMCAN Tx Event FIFO StatusGo
7ChMCAN_TXEFAMCAN Tx Event FIFO AcknowledgeGo

Complex bit access types are encoded to fit into small table cells. Table 35-31 shows the codes that are used for access types in this section.

Table 35-31 MCAN_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCR
C		Read
to Clear
RSR
S		Read
to Set
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SQW
1S
Q		Write
1 to set
Qualified. A condition must be met for this operation to occur.
WQW
Q		Write
Qualified. A condition must be met for this operation to occur.
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

35.7.3.1 MCAN_CREL Register (Offset = 0h) [Reset = 32380608h]

MCAN_CREL is shown in Figure 35-36 and described in Table 35-32.

Return to the Summary Table.

MCAN Core Release Register

Figure 35-36 MCAN_CREL Register
31302928272625242322212019181716
RELSTEPSUBSTEPYEAR
R-3hR-2hR-3hR-8h
1514131211109876543210
MONDAY
R-6hR-8h
Table 35-32 MCAN_CREL Register Field Descriptions
BitFieldTypeResetDescription
31-28RELR3hCore Release. One digit, BCD-coded.

Reset type: SYSRSn

27-24STEPR2hStep of Core Release. One digit, BCD-coded.

Reset type: SYSRSn

23-20SUBSTEPR3hSub-Step of Core Release. One digit, BCD-coded.

Reset type: SYSRSn

19-16YEARR8hTime Stamp Year. One digit, BCD-coded.

Reset type: SYSRSn

15-8MONR6hTime Stamp Month. Two digits, BCD-coded.

Reset type: SYSRSn

7-0DAYR8hTime Stamp Day. Two digits, BCD-coded.

Reset type: SYSRSn

35.7.3.2 MCAN_ENDN Register (Offset = 2h) [Reset = 87654321h]

MCAN_ENDN is shown in Figure 35-37 and described in Table 35-33.

Return to the Summary Table.

MCAN Endian Register

Figure 35-37 MCAN_ENDN Register
313029282726252423222120191817161514131211109876543210
ETV
R-87654321h
Table 35-33 MCAN_ENDN Register Field Descriptions
BitFieldTypeResetDescription
31-0ETVR87654321hEndianess Test Value. Reading the constant value maintained in this register allows software to determine the endianess of the host CPU.

Reset type: SYSRSn

35.7.3.3 MCAN_DBTP Register (Offset = 6h) [Reset = 00000A33h]

MCAN_DBTP is shown in Figure 35-38 and described in Table 35-34.

Return to the Summary Table.

This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 m_can_cclk periods. tq = (DBRP + 1) mtq.

DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2.

Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.

The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Figure 35-38 MCAN_DBTP Register
3130292827262524
RESERVED
R-0h
2322212019181716
TDCRESERVEDDBRP
R/WQ-0hR-0hR/WQ-0h
15141312111098
RESERVEDDTSEG1
R-0hR/WQ-Ah
76543210
DTSEG2DSJW
R/WQ-3hR/WQ-3h
Table 35-34 MCAN_DBTP Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23TDCR/WQ0hTransmitter Delay Compensation
0 Transmitter Delay Compensation disabled
1 Transmitter Delay Compensation enabled

+I107

Reset type: SYSRSn

22-21RESERVEDR0hReserved
20-16DBRPR/WQ0hData Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

15-13RESERVEDR0hReserved
12-8DTSEG1R/WQAhData Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

7-4DTSEG2R/WQ3hData Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

3-0DSJWR/WQ3hData Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

35.7.3.4 MCAN_TEST Register (Offset = 8h) [Reset = 000000X0h]

MCAN_TEST is shown in Figure 35-39 and described in Table 35-35.

Return to the Summary Table.

Write access to the Test Register has to be enabled by setting bit CCCR.TEST to '1'. All Test Register functions are set to their reset values when bit CCCR.TEST is reset.

Loop Back Mode and software control of the internal CAN TX pin are hardware test modes. Programming of
TX != '00' may disturb the message transfer on the CAN bus.

Figure 35-39 MCAN_TEST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RXTXLBCKRESERVED
R-XhR/WQ-0hR/WQ-0hR-0h
Table 35-35 MCAN_TEST Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7RXRXhReceive Pin. Monitors the actual value of the CAN receive pin.
0 The CAN bus is dominant (CAN RX pin = '0')
1 The CAN bus is recessive (CAN RX pin = '1')

Reset type: SYSRSn

6-5TXR/WQ0hControl of Transmit Pin
00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time
01 Sample Point can be monitored at CAN TX pin
10 Dominant ('0') level at CAN TX pin
11 Recessive ('1') at CAN TX pin

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

4LBCKR/WQ0hLoop Back Mode
0 Reset value, Loop Back Mode is disabled
1 Loop Back Mode is enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

3-0RESERVEDR0hReserved

35.7.3.5 MCAN_RWD Register (Offset = Ah) [Reset = 00000000h]

MCAN_RWD is shown in Figure 35-40 and described in Table 35-36.

Return to the Summary Table.

MCAN RAM Watchdog

Figure 35-40 MCAN_RWD Register
313029282726252423222120191817161514131211109876543210
RESERVEDWDVWDC
R-0hR-0hR/WQ-0h
Table 35-36 MCAN_RWD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8WDVR0hWatchdog Value. Actual Message RAM Watchdog Counter Value.

The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the MCAN's Generic Controller Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock.

Reset type: SYSRSn

7-0WDCR/WQ0hWatchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is disabled.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

35.7.3.6 MCAN_CCCR Register (Offset = Ch) [Reset = 00000001h]

MCAN_CCCR is shown in Figure 35-41 and described in Table 35-37.

Return to the Summary Table.

MCAN CC Control Register

Figure 35-41 MCAN_CCCR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
NISOTXPEFBIPXHDRESERVEDBRSEFDOE
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR-0hR/WQ-0hR/WQ-0h
76543210
TESTDARMONCSRCSAASMCCEINIT
R/W1SQ-0hR/WQ-0hR/W1SQ-0hR/W-0hR-0hR/W1SQ-0hR/WQ-0hR/W-1h
Table 35-37 MCAN_CCCR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15NISOR/WQ0hNon ISO Operation. If this bit is set, the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.
0 CAN FD frame format according to ISO 11898-1:2015
1 CAN FD frame format according to Bosch CAN FD Specification V1.0

Reset type: SYSRSn

14TXPR/WQ0hTransmit Pause. If this bit is set, the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame.
0 Transmit pause disabled
1 Transmit pause enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

13EFBIR/WQ0hEdge Filtering during Bus Integration
0 Edge filtering disabled
1 Two consecutive dominant tq required to detect an edge for hard synchronization

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

12PXHDR/WQ0hProtocol Exception Handling Disable
0 Protocol exception handling enabled
1 Protocol exception handling disabled
Note: When protocol exception handling is disabled, the MCAN will transmit an error frame when it detects a protocol exception condition.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

11-10RESERVEDR0hReserved
9BRSER/WQ0hBit Rate Switch Enable
0 Bit rate switching for transmissions disabled
1 Bit rate switching for transmissions enabled
Note: When CAN FD operation is disabled FDOE = '0', BRSE is not evaluated.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

8FDOER/WQ0hFlexible Datarate Operation Enable
0 FD operation disabled
1 FD operation enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

7TESTR/W1SQ0hTest Mode Enable
0 Normal operation, register TEST holds reset values
1 Test Mode, write access to register TEST enabled

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

6DARR/WQ0hDisable Automatic Retransmission
0 Automatic retransmission of messages not transmitted successfully enabled
1 Automatic retransmission disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

5MONR/W1SQ0hBus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time.
0 Bus Monitoring Mode is disabled
1 Bus Monitoring Mode is enabled

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

4CSRR/W0hClock Stop Request
0 No clock stop is requested
1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle.

Reset type: SYSRSn

3CSAR0hClock Stop Acknowledge
0 No clock stop acknowledged
1 MCAN may be set in power down by stopping the Host and CAN clocks

Reset type: SYSRSn

2ASMR/W1SQ0hRestricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time.
0 Normal CAN operation
1 Restricted Operation Mode active

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

1CCER/WQ0hConfiguration Change Enable
0 The CPU has no write access to the protected configuration registers
1 The CPU has write access to the protected configuration registers (while CCCR.INIT = '1')

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

0INITR/W1hInitialization
0 Normal Operation
1 Initialization is started
Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value.

Reset type: SYSRSn

35.7.3.7 MCAN_NBTP Register (Offset = Eh) [Reset = 06000A03h]

MCAN_NBTP is shown in Figure 35-42 and described in Table 35-38.

Return to the Summary Table.

This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 m_can_cclk periods. tq = (NBRP + 1) mtq.

NTSEG1 is the sum of Prop_Seg and Phase_Seg1. NTSEG2 is Phase_Seg2.

Therefore the length of the bit time is (programmed values) [NTSEG1 + NTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.

The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Note: With a CAN clock of 8 MHz, the reset value of 0x06000A03 configures the MCAN for a bit rate of 500 kBit/s.

Figure 35-42 MCAN_NBTP Register
3130292827262524
NSJWNBRP
R/WQ-3hR/WQ-0h
2322212019181716
NBRP
R/WQ-0h
15141312111098
NTSEG1
R/WQ-Ah
76543210
RESERVEDNTSEG2
R-0hR/WQ-3h
Table 35-38 MCAN_NBTP Register Field Descriptions
BitFieldTypeResetDescription
31-25NSJWR/WQ3hNominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

24-16NBRPR/WQ0hNominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

15-8NTSEG1R/WQAhNominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

7RESERVEDR0hReserved
6-0NTSEG2R/WQ3hNominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

35.7.3.8 MCAN_TSCC Register (Offset = 10h) [Reset = 00000000h]

MCAN_TSCC is shown in Figure 35-43 and described in Table 35-39.

Return to the Summary Table.

MCAN Timestamp Counter Configuration

Figure 35-43 MCAN_TSCC Register
31302928272625242322212019181716
RESERVEDTCP
R-0hR/WQ-0h
1514131211109876543210
RESERVEDTSS
R-0hR/WQ-0h
Table 35-39 MCAN_TSCC Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16TCPR/WQ0hTimestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Note: With CAN FD an external counter is required for timestamp generation (TSS = '10').

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

15-2RESERVEDR0hReserved
1-0TSSR/WQ0hTimestamp Select
00 Timestamp counter value always 0x0000
01 Timestamp counter value incremented according to TCP
10 External timestamp counter value used
11 Same as '00'

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

35.7.3.9 MCAN_TSCV Register (Offset = 12h) [Reset = 00000000h]

MCAN_TSCV is shown in Figure 35-44 and described in Table 35-40.

Return to the Summary Table.

MCAN Timestamp Counter Value

Figure 35-44 MCAN_TSCV Register
313029282726252423222120191817161514131211109876543210
RESERVEDTSC
R-0hR/W-0h
Table 35-40 MCAN_TSCV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0TSCR/W0hTimestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times, [1...16], depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the External Timestamp Counter value, and a write access has no impact.

Note: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not
caused by write access to MCAN_TSCV.

Reset type: SYSRSn

35.7.3.10 MCAN_TOCC Register (Offset = 14h) [Reset = FFFF0000h]

MCAN_TOCC is shown in Figure 35-45 and described in Table 35-41.

Return to the Summary Table.

MCAN Timeout Counter Configuration

Figure 35-45 MCAN_TOCC Register
3130292827262524
TOP
R/WQ-FFFFh
2322212019181716
TOP
R/WQ-FFFFh
15141312111098
RESERVED
R-0h
76543210
RESERVEDTOSETOC
R-0hR/WQ-0hR/WQ-0h
Table 35-41 MCAN_TOCC Register Field Descriptions
BitFieldTypeResetDescription
31-16TOPR/WQFFFFhTimeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

15-3RESERVEDR0hReserved
2-1TOSR/WQ0hTimeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored.
00 Continuous operation
01 Timeout controlled by Tx Event FIFO
10 Timeout controlled by Rx FIFO 0
11 Timeout controlled by Rx FIFO 1

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

0ETOCR/WQ0hEnable Timeout Counter
0 Timeout Counter disabled
1 Timeout Counter enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

35.7.3.11 MCAN_TOCV Register (Offset = 16h) [Reset = 0000FFFFh]

MCAN_TOCV is shown in Figure 35-46 and described in Table 35-42.

Return to the Summary Table.

MCAN Timeout Counter Value

Figure 35-46 MCAN_TOCV Register
313029282726252423222120191817161514131211109876543210
RESERVEDTOC
R-0hR/W-FFFFh
Table 35-42 MCAN_TOCV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0TOCR/WFFFFhTimeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, [1...16], depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS.

Reset type: SYSRSn

35.7.3.12 MCAN_ECR Register (Offset = 20h) [Reset = 00000000h]

MCAN_ECR is shown in Figure 35-47 and described in Table 35-43.

Return to the Summary Table.

MCAN Error Counter Register

Figure 35-47 MCAN_ECR Register
31302928272625242322212019181716
RESERVEDCEL
R-0hRC-0h
1514131211109876543210
RPRECTEC
R-0hR-0hR-0h
Table 35-43 MCAN_ECR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16CELRC0hCAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF
the next increment of TEC or REC sets interrupt flag IR.ELO.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

Reset type: SYSRSn

15RPR0hReceive Error Passive
0 The Receive Error Counter is below the error passive level of 128
1 The Receive Error Counter has reached the error passive level of 128

Reset type: SYSRSn

14-8RECR0hReceive Error Counter. Actual state of the Receive Error Counter, values between 0 and 127.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

Reset type: SYSRSn

7-0TECR0hTransmit Error Counter. Actual state of the Transmit Error Counter, values between 0 and 255.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

Reset type: SYSRSn

35.7.3.13 MCAN_PSR Register (Offset = 22h) [Reset = 00000707h]

MCAN_PSR is shown in Figure 35-48 and described in Table 35-44.

Return to the Summary Table.

MCAN Protocol Status Register

Figure 35-48 MCAN_PSR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTDCV
R-0hR-0h
15141312111098
RESERVEDPXERFDFRBRSRESIDLEC
R-0hRC-0hRC-0hRC-0hRC-0hRS-7h
76543210
BOEWEPACTLEC
R-0hR-0hR-0hR-0hRS-7h
Table 35-44 MCAN_PSR Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved
22-16TDCVR0hTransmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.

Reset type: SYSRSn

15RESERVEDR0hReserved
14PXERC0hProtocol Exception Event
0 No protocol exception event occurred since last read access
1 Protocol exception event occurred

Reset type: SYSRSn

13RFDFRC0hReceived a CAN FD Message. This bit is set independent of acceptance filtering.
0 Since this bit was reset by the CPU, no CAN FD message has been received
1 Message in CAN FD format with FDF flag set has been received

Reset type: SYSRSn

12RBRSRC0hBRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering.
0 Last received CAN FD message did not have its BRS flag set
1 Last received CAN FD message had its BRS flag set

Reset type: SYSRSn

11RESIRC0hESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering.
0 Last received CAN FD message did not have its ESI flag set
1 Last received CAN FD message had its ESI flag set

Reset type: SYSRSn

10-8DLECRS7hData Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.

Reset type: SYSRSn

7BOR0hBus_Off Status
0 The M_CAN is not Bus_Off
1 The M_CAN is in Bus_Off state

Reset type: SYSRSn

6EWR0hWarning Status
0 Both error counters are below the Error_Warning limit of 96
1 At least one of error counter has reached the Error_Warning limit of 96

Reset type: SYSRSn

5EPR0hError Passive
0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected
1 The M_CAN is in the Error_Passive state

Reset type: SYSRSn

4-3ACTR0hNode Activity. Monitors the module's CAN communication state.
00 Synchronizing - node is synchronizing on CAN communication
01 Idle - node is neither receiver nor transmitter
10 Receiver - node is operating as receiver
11 Transmitter - node is operating as transmitter

Note: ACT is set to '00' by a Protocol Exception Event.

Reset type: SYSRSn

2-0LECRS7hLast Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
0 No Error: No error occurred since LEC has been reset by successful reception or transmission.
1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
2 Form Error: A fixed format part of a received frame has the wrong format.
3 AckError: The message transmitted by the MCAN was not acknowledged by another node.
4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.
5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register.

Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences.

Reset type: SYSRSn

35.7.3.14 MCAN_TDCR Register (Offset = 24h) [Reset = 00000000h]

MCAN_TDCR is shown in Figure 35-49 and described in Table 35-45.

Return to the Summary Table.

MCAN Transmitter Delay Compensation Register

Figure 35-49 MCAN_TDCR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTDCO
R-0hR/WQ-0h
76543210
RESERVEDTDCF
R-0hR/WQ-0h
Table 35-45 MCAN_TDCR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15RESERVEDR0hReserved
14-8TDCOR/WQ0hTransmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

7RESERVEDR0hReserved
6-0TDCFR/WQ0hTransmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

35.7.3.15 MCAN_IR Register (Offset = 28h) [Reset = 80000000h]

MCAN_IR is shown in Figure 35-50 and described in Table 35-46.

Return to the Summary Table.

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. Aflag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. Ahard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signalled.

Figure 35-50 MCAN_IR Register
3130292827262524
RESERVEDRESERVEDARAPEDPEAWDIBOEW
R-1hR-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
2322212019181716
EPELOBEURESERVEDDRXTOOMRAFTSW
R/W1C-0hR/W1C-0hR/W1C-0hR-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
TEFLTEFFTEFWTEFNTFETCFTCHPM
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
RF1LRF1FRF1WRF1NRF0LRF0FRF0WRF0N
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 35-46 MCAN_IR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR1hReserved
30RESERVEDR0hReserved
29ARAR/W1C0hAccess to Reserved Address
0 No access to reserved address occurred
1 Access to reserved address occurred

Reset type: SYSRSn

28PEDR/W1C0hProtocol Error in Data Phase (Data Bit Time is used)
0 No protocol error in data phase
1 Protocol error in data phase detected (PSR.DLEC != 0,7)

Reset type: SYSRSn

27PEAR/W1C0hProtocol Error in Arbitration Phase (Nominal Bit Time is used)
0 No protocol error in arbitration phase
1 Protocol error in arbitration phase detected (PSR.LEC != 0,7)

Reset type: SYSRSn

26WDIR/W1C0hWatchdog Interrupt
0 No Message RAM Watchdog event occurred
1 Message RAM Watchdog event due to missing READY

Reset type: SYSRSn

25BOR/W1C0hBus_Off Status
0 Bus_Off status unchanged
1 Bus_Off status changed

Reset type: SYSRSn

24EWR/W1C0hWarning Status
0 Error_Warning status unchanged
1 Error_Warning status changed

Reset type: SYSRSn

23EPR/W1C0hError Passive
0 Error_Passive status unchanged
1 Error_Passive status changed

Reset type: SYSRSn

22ELOR/W1C0hError Logging Overflow
0 CAN Error Logging Counter did not overflow
1 Overflow of CAN Error Logging Counter occurred

Reset type: SYSRSn

21BEUR/W1C0hBit Error Uncorrected. Message RAM bit error detected, uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data.
0 No bit error detected when reading from Message RAM
1 Bit error detected, uncorrected (e.g. parity logic)

Reset type: SYSRSn

20RESERVEDR0hReserved
19DRXR/W1C0hMessage Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer.
0 No Rx Buffer updated
1 At least one received message stored into an Rx Buffer

Reset type: SYSRSn

18TOOR/W1C0hTimeout Occurred
0 No timeout
1 Timeout reached

Reset type: SYSRSn

17MRAFR/W1C0hMessage RAM Access Failure. The flag is set, when the Rx Handler:
- has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
- was not able to write a message to the Message RAM. In this case message storage is aborted.

In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.

The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation Mode. To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM.
0 No Message RAM access failure occurred
1 Message RAM access failure occurred

Reset type: SYSRSn

16TSWR/W1C0hTimestamp Wraparound
0 No timestamp counter wrap-around
1 Timestamp counter wrapped around

Reset type: SYSRSn

15TEFLR/W1C0hTx Event FIFO Element Lost
0 No Tx Event FIFO element lost
1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero

Reset type: SYSRSn

14TEFFR/W1C0hTx Event FIFO Full
0 Tx Event FIFO not full
1 Tx Event FIFO full

Reset type: SYSRSn

13TEFWR/W1C0hTx Event FIFO Watermark Reached
0 Tx Event FIFO fill level below watermark
1 Tx Event FIFO fill level reached watermark

Reset type: SYSRSn

12TEFNR/W1C0hTx Event FIFO New Entry
0 Tx Event FIFO unchanged
1 Tx Handler wrote Tx Event FIFO element

Reset type: SYSRSn

11TFER/W1C0hTx FIFO Empty
0 Tx FIFO non-empty
1 Tx FIFO empty

Reset type: SYSRSn

10TCFR/W1C0hTransmission Cancellation Finished
0 No transmission cancellation finished
1 Transmission cancellation finished

Reset type: SYSRSn

9TCR/W1C0hTransmission Completed
0 No transmission completed
1 Transmission completed

Reset type: SYSRSn

8HPMR/W1C0hHigh Priority Message
0 No high priority message received
1 High priority message received

Reset type: SYSRSn

7RF1LR/W1C0hRx FIFO 1 Message Lost
0 No Rx FIFO 1 message lost
1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero

Reset type: SYSRSn

6RF1FR/W1C0hRx FIFO 1 Full
0 Rx FIFO 1 not full
1 Rx FIFO 1 full

Reset type: SYSRSn

5RF1WR/W1C0hRx FIFO 1 Watermark Reached
0 Rx FIFO 1 fill level below watermark
1 Rx FIFO 1 fill level reached watermark

Reset type: SYSRSn

4RF1NR/W1C0hRx FIFO 1 New Message
0 No new message written to Rx FIFO 1
1 New message written to Rx FIFO 1

Reset type: SYSRSn

3RF0LR/W1C0hRx FIFO 0 Message Lost
0 No Rx FIFO 0 message lost
1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero

Reset type: SYSRSn

2RF0FR/W1C0hRx FIFO 0 Full
0 Rx FIFO 0 not full
1 Rx FIFO 0 full

Reset type: SYSRSn

1RF0WR/W1C0hRx FIFO 0 Watermark Reached
0 Rx FIFO 0 fill level below watermark
1 Rx FIFO 0 fill level reached watermark

Reset type: SYSRSn

0RF0NR/W1C0hRx FIFO 0 New Message
0 No new message written to Rx FIFO 0
1 New message written to Rx FIFO 0

Reset type: SYSRSn

35.7.3.16 MCAN_IE Register (Offset = 2Ah) [Reset = 00000000h]

MCAN_IE is shown in Figure 35-51 and described in Table 35-47.

Return to the Summary Table.

MCAN Interrupt Enable

Figure 35-51 MCAN_IE Register
3130292827262524
RESERVEDARAEPEDEPEAEWDIEBOEEWE
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
EPEELOEBEUEBECEDRXETOOEMRAFETSWE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TEFLETEFFETEFWETEFNETFEETCFETCEHPME
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RF1LERF1FERF1WERF1NERF0LERF0FERF0WERF0NE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 35-47 MCAN_IE Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29ARAER/W0hAccess to Reserved Address Enable

Reset type: SYSRSn

28PEDER/W0hProtocol Error in Data Phase Enable

Reset type: SYSRSn

27PEAER/W0hProtocol Error in Arbitration Phase Enable

Reset type: SYSRSn

26WDIER/W0hWatchdog Interrupt Enable

Reset type: SYSRSn

25BOER/W0hBus_Off Status Enable

Reset type: SYSRSn

24EWER/W0hWarning Status Enable

Reset type: SYSRSn

23EPER/W0hError Passive Enable

Reset type: SYSRSn

22ELOER/W0hError Logging Overflow Enable

Reset type: SYSRSn

21BEUER/W0hBit Error Uncorrected Enable

Reset type: SYSRSn

20BECER/W0hBit Error Corrected Enable

A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave this bit cleared to '0'.

Reset type: SYSRSn

19DRXER/W0hMessage Stored to Dedicated Rx Buffer Enable

Reset type: SYSRSn

18TOOER/W0hTimeout Occurred Enable

Reset type: SYSRSn

17MRAFER/W0hMessage RAM Access Failure Enable

Reset type: SYSRSn

16TSWER/W0hTimestamp Wraparound Enable

Reset type: SYSRSn

15TEFLER/W0hTx Event FIFO Element Lost Enable

Reset type: SYSRSn

14TEFFER/W0hTx Event FIFO Full Enable

Reset type: SYSRSn

13TEFWER/W0hTx Event FIFO Watermark Reached Enable

Reset type: SYSRSn

12TEFNER/W0hTx Event FIFO New Entry Enable

Reset type: SYSRSn

11TFEER/W0hTx FIFO Empty Enable

Reset type: SYSRSn

10TCFER/W0hTransmission Cancellation Finished Enable

Reset type: SYSRSn

9TCER/W0hTransmission Completed Enable

Reset type: SYSRSn

8HPMER/W0hHigh Priority Message Enable

Reset type: SYSRSn

7RF1LER/W0hRx FIFO 1 Message Lost Enable

Reset type: SYSRSn

6RF1FER/W0hRx FIFO 1 Full Enable

Reset type: SYSRSn

5RF1WER/W0hRx FIFO 1 Watermark Reached Enable

Reset type: SYSRSn

4RF1NER/W0hRx FIFO 1 New Message Enable

Reset type: SYSRSn

3RF0LER/W0hRx FIFO 0 Message Lost Enable

Reset type: SYSRSn

2RF0FER/W0hRx FIFO 0 Full Enable

Reset type: SYSRSn

1RF0WER/W0hRx FIFO 0 Watermark Reached Enable

Reset type: SYSRSn

0RF0NER/W0hRx FIFO 0 New Message Enable

Reset type: SYSRSn

35.7.3.17 MCAN_ILS Register (Offset = 2Ch) [Reset = 00000000h]

MCAN_ILS is shown in Figure 35-52 and described in Table 35-48.

Return to the Summary Table.

The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE.EINT0 and ILE.EINT1.

Figure 35-52 MCAN_ILS Register
3130292827262524
RESERVEDARALPEDLPEALWDILBOLEWL
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
EPLELOLBEULBECLDRXLTOOLMRAFLTSWL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TEFLLTEFFLTEFWLTEFNLTFELTCFLTCLHPML
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RF1LLRF1FLRF1WLRF1NLRF0LLRF0FLRF0WLRF0NL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 35-48 MCAN_ILS Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29ARALR/W0hAccess to Reserved Address Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

28PEDLR/W0hProtocol Error in Data Phase Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

27PEALR/W0hProtocol Error in Arbitration Phase Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

26WDILR/W0hWatchdog Interrupt Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

25BOLR/W0hBus_Off Status Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

24EWLR/W0hWarning Status Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

23EPLR/W0hError Passive Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

22ELOLR/W0hError Logging Overflow Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

21BEULR/W0hBit Error Uncorrected Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

20BECLR/W0hBit Error Corrected Line

A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave the MCAN_IE.BECE bit cleared to '0' (disabled), thereby relegating this bit to not applicable.

Reset type: SYSRSn

19DRXLR/W0hMessage Stored to Dedicated Rx Buffer Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

18TOOLR/W0hTimeout Occurred Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

17MRAFLR/W0hMessage RAM Access Failure Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

16TSWLR/W0hTimestamp Wraparound Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

15TEFLLR/W0hTx Event FIFO Element Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

14TEFFLR/W0hTx Event FIFO Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

13TEFWLR/W0hTx Event FIFO Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

12TEFNLR/W0hTx Event FIFO New Entry Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

11TFELR/W0hTx FIFO Empty Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

10TCFLR/W0hTransmission Cancellation Finished Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

9TCLR/W0hTransmission Completed Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

8HPMLR/W0hHigh Priority Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

7RF1LLR/W0hRx FIFO 1 Message Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

6RF1FLR/W0hRx FIFO 1 Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

5RF1WLR/W0hRx FIFO 1 Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

4RF1NLR/W0hRx FIFO 1 New Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

3RF0LLR/W0hRx FIFO 0 Message Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

2RF0FLR/W0hRx FIFO 0 Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

1RF0WLR/W0hRx FIFO 0 Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

0RF0NLR/W0hRx FIFO 0 New Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

Reset type: SYSRSn

35.7.3.18 MCAN_ILE Register (Offset = 2Eh) [Reset = 00000000h]

MCAN_ILE is shown in Figure 35-53 and described in Table 35-49.

Return to the Summary Table.

MCAN Interrupt Line Enable

Figure 35-53 MCAN_ILE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEINT1EINT0
R-0hR/W-0hR/W-0h
Table 35-49 MCAN_ILE Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1EINT1R/W0hEnable Interrupt Line 1
0 Interrupt Line 1 is disabled
1 Interrupt Line 1 is enabled

Reset type: SYSRSn

0EINT0R/W0hEnable Interrupt Line 0
0 Interrupt Line 0 is disabled
1 Interrupt Line 0 is enabled

Reset type: SYSRSn

35.7.3.19 MCAN_GFC Register (Offset = 40h) [Reset = 00000000h]

MCAN_GFC is shown in Figure 35-54 and described in Table 35-50.

Return to the Summary Table.

MCAN Global Filter Configuration

Figure 35-54 MCAN_GFC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDANFSANFERRFSRRFE
R-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
Table 35-50 MCAN_GFC Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-4ANFSR/WQ0hAccept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated.
00 Accept in Rx FIFO 0
01 Accept in Rx FIFO 1
10 Reject
11 Reject

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

3-2ANFER/WQ0hAccept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated.
00 Accept in Rx FIFO 0
01 Accept in Rx FIFO 1
10 Reject
11 Reject

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

1RRFSR/WQ0hReject Remote Frames Standard
0 Filter remote frames with 11-bit standard IDs
1 Reject all remote frames with 11-bit standard IDs

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

0RRFER/WQ0hReject Remote Frames Extended
0 Filter remote frames with 29-bit extended IDs
1 Reject all remote frames with 29-bit extended IDs

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

35.7.3.20 MCAN_SIDFC Register (Offset = 42h) [Reset = 00000000h]

MCAN_SIDFC is shown in Figure 35-55 and described in Table 35-51.

Return to the Summary Table.

MCAN Standard ID Filter Configuration

Figure 35-55 MCAN_SIDFC Register
3130292827262524
RESERVED
R-0h
2322212019181716
LSS
R/WQ-0h
15141312111098
FLSSA
R/WQ-0h
76543210
FLSSARESERVED
R/WQ-0hR-0h
Table 35-51 MCAN_SIDFC Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16LSSR/WQ0hList Size Standard
0 No standard Message ID filter
1-128 Number of standard Message ID filter elements
>128 Values greater than 128 are interpreted as 128

Reset type: SYSRSn

15-2FLSSAR/WQ0hFilter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address).

Reset type: SYSRSn

1-0RESERVEDR0hReserved

35.7.3.21 MCAN_XIDFC Register (Offset = 44h) [Reset = 00000000h]

MCAN_XIDFC is shown in Figure 35-56 and described in Table 35-52.

Return to the Summary Table.

MCAN Extended ID Filter Configuration

Figure 35-56 MCAN_XIDFC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDLSE
R-0hR/WQ-0h
15141312111098
FLESA
R/WQ-0h
76543210
FLESARESERVED
R/WQ-0hR-0h
Table 35-52 MCAN_XIDFC Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved
22-16LSER/WQ0hList Size Extended
0 No extended Message ID filter
1-64 Number of extended Message ID filter elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

15-2FLESAR/WQ0hFilter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

1-0RESERVEDR0hReserved

35.7.3.22 MCAN_XIDAM Register (Offset = 48h) [Reset = 1FFFFFFFh]

MCAN_XIDAM is shown in Figure 35-57 and described in Table 35-53.

Return to the Summary Table.

MCAN Extended ID and Mask

Figure 35-57 MCAN_XIDAM Register
31302928272625242322212019181716
RESERVEDEIDM
R-0hR/WQ-1FFFFFFFh
1514131211109876543210
EIDM
R/WQ-1FFFFFFFh
Table 35-53 MCAN_XIDAM Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-0EIDMR/WQ1FFFFFFFhExtended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

35.7.3.23 MCAN_HPMS Register (Offset = 4Ah) [Reset = 00000000h]

MCAN_HPMS is shown in Figure 35-58 and described in Table 35-54.

Return to the Summary Table.

This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.

Figure 35-58 MCAN_HPMS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
FLSTFIDX
R-0hR-0h
76543210
MSIBIDX
R-0hR-0h
Table 35-54 MCAN_HPMS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15FLSTR0hFilter List. Indicates the filter list of the matching filter element.
0 Standard Filter List
1 Extended Filter List

Reset type: SYSRSn

14-8FIDXR0hFilter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.

Reset type: SYSRSn

7-6MSIR0hMessage Storage Indicator
00 No FIFO selected
01 FIFO message lost
10 Message stored in FIFO 0
11 Message stored in FIFO 1

Reset type: SYSRSn

5-0BIDXR0hBuffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'.

Reset type: SYSRSn

35.7.3.24 MCAN_NDAT1 Register (Offset = 4Ch) [Reset = 00000000h]

MCAN_NDAT1 is shown in Figure 35-59 and described in Table 35-55.

Return to the Summary Table.

MCAN New Data 1

Figure 35-59 MCAN_NDAT1 Register
3130292827262524
ND31ND30ND29ND28ND27ND26ND25ND24
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
2322212019181716
ND23ND22ND21ND20ND19ND18ND17ND16
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
ND15ND14ND13ND12ND11ND10ND9ND8
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
ND7ND6ND5ND4ND3ND2ND1ND0
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 35-55 MCAN_NDAT1 Register Field Descriptions
BitFieldTypeResetDescription
31ND31R/W1C0hNew Data RX Buffer 31
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

30ND30R/W1C0hNew Data RX Buffer 30
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

29ND29R/W1C0hNew Data RX Buffer 29
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

28ND28R/W1C0hNew Data RX Buffer 28
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

27ND27R/W1C0hNew Data RX Buffer 27
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

26ND26R/W1C0hNew Data RX Buffer 26
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

25ND25R/W1C0hNew Data RX Buffer 25
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

24ND24R/W1C0hNew Data RX Buffer 24
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

23ND23R/W1C0hNew Data RX Buffer 23
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

22ND22R/W1C0hNew Data RX Buffer 22
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

21ND21R/W1C0hNew Data RX Buffer 21
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

20ND20R/W1C0hNew Data RX Buffer 20
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

19ND19R/W1C0hNew Data RX Buffer 19
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

18ND18R/W1C0hNew Data RX Buffer 18
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

17ND17R/W1C0hNew Data RX Buffer 17
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

16ND16R/W1C0hNew Data RX Buffer 16
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

15ND15R/W1C0hNew Data RX Buffer 15
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

14ND14R/W1C0hNew Data RX Buffer 14
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

13ND13R/W1C0hNew Data RX Buffer 13
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

12ND12R/W1C0hNew Data RX Buffer 12
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

11ND11R/W1C0hNew Data RX Buffer 11
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

10ND10R/W1C0hNew Data RX Buffer 10
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

9ND9R/W1C0hNew Data RX Buffer 9
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

8ND8R/W1C0hNew Data RX Buffer 8
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

7ND7R/W1C0hNew Data RX Buffer 7
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

6ND6R/W1C0hNew Data RX Buffer 6
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

5ND5R/W1C0hNew Data RX Buffer 5
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

4ND4R/W1C0hNew Data RX Buffer 4
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

3ND3R/W1C0hNew Data RX Buffer 3
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

2ND2R/W1C0hNew Data RX Buffer 2
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

1ND1R/W1C0hNew Data RX Buffer 1
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

0ND0R/W1C0hNew Data RX Buffer 0
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

35.7.3.25 MCAN_NDAT2 Register (Offset = 4Eh) [Reset = 00000000h]

MCAN_NDAT2 is shown in Figure 35-60 and described in Table 35-56.

Return to the Summary Table.

MCAN New Data 2

Figure 35-60 MCAN_NDAT2 Register
3130292827262524
ND63ND62ND61ND60ND59ND58ND57ND56
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
2322212019181716
ND55ND54ND53ND52ND51ND50ND49ND48
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
15141312111098
ND47ND46ND45ND44ND43ND42ND41ND40
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
76543210
ND39ND38ND37ND36ND35ND34ND33ND32
R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h
Table 35-56 MCAN_NDAT2 Register Field Descriptions
BitFieldTypeResetDescription
31ND63R/W1C0hNew Data RX Buffer 63
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

30ND62R/W1C0hNew Data RX Buffer 62
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

29ND61R/W1C0hNew Data RX Buffer 61
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

28ND60R/W1C0hNew Data RX Buffer 60
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

27ND59R/W1C0hNew Data RX Buffer 59
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

26ND58R/W1C0hNew Data RX Buffer 58
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

25ND57R/W1C0hNew Data RX Buffer 57
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

24ND56R/W1C0hNew Data RX Buffer 56
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

23ND55R/W1C0hNew Data RX Buffer 55
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

22ND54R/W1C0hNew Data RX Buffer 54
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

21ND53R/W1C0hNew Data RX Buffer 53
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

20ND52R/W1C0hNew Data RX Buffer 52
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

19ND51R/W1C0hNew Data RX Buffer 51
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

18ND50R/W1C0hNew Data RX Buffer 50
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

17ND49R/W1C0hNew Data RX Buffer 49
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

16ND48R/W1C0hNew Data RX Buffer 48
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

15ND47R/W1C0hNew Data RX Buffer 47
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

14ND46R/W1C0hNew Data RX Buffer 46
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

13ND45R/W1C0hNew Data RX Buffer 45
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

12ND44R/W1C0hNew Data RX Buffer 44
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

11ND43R/W1C0hNew Data RX Buffer 43
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

10ND42R/W1C0hNew Data RX Buffer 42
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

9ND41R/W1C0hNew Data RX Buffer 41
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

8ND40R/W1C0hNew Data RX Buffer 40
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

7ND39R/W1C0hNew Data RX Buffer 39
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

6ND38R/W1C0hNew Data RX Buffer 38
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

5ND37R/W1C0hNew Data RX Buffer 37
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

4ND36R/W1C0hNew Data RX Buffer 36
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

3ND35R/W1C0hNew Data RX Buffer 35
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

2ND34R/W1C0hNew Data RX Buffer 34
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

1ND33R/W1C0hNew Data RX Buffer 33
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

0ND32R/W1C0hNew Data RX Buffer 32
0 Rx Buffer not updated
1 Rx Buffer updated from new message

Reset type: SYSRSn

35.7.3.26 MCAN_RXF0C Register (Offset = 50h) [Reset = 00000000h]

MCAN_RXF0C is shown in Figure 35-61 and described in Table 35-57.

Return to the Summary Table.

MCAN Rx FIFO 0 Configuration

Figure 35-61 MCAN_RXF0C Register
3130292827262524
F0OMF0WM
R/WQ-0hR/WQ-0h
2322212019181716
RESERVEDF0S
R-0hR/WQ-0h
15141312111098
F0SA
R/WQ-0h
76543210
F0SARESERVED
R/WQ-0hR-0h
Table 35-57 MCAN_RXF0C Register Field Descriptions
BitFieldTypeResetDescription
31F0OMR/WQ0hFIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode.
0 FIFO 0 blocking mode
1 FIFO 0 overwrite mode

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

30-24F0WMR/WQ0hRx FIFO 0 Watermark
0 Watermark interrupt disabled
1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W)
>64 Watermark interrupt disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

23RESERVEDR0hReserved
22-16F0SR/WQ0hRx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1.
0 No Rx FIFO 0
1-64 Number of Rx FIFO 0 elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

15-2F0SAR/WQ0hRx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

1-0RESERVEDR0hReserved

35.7.3.27 MCAN_RXF0S Register (Offset = 52h) [Reset = 00000000h]

MCAN_RXF0S is shown in Figure 35-62 and described in Table 35-58.

Return to the Summary Table.

MCAN Rx FIFO 0 Status

Figure 35-62 MCAN_RXF0S Register
3130292827262524
RESERVEDRF0LF0F
R-0hR-0hR-0h
2322212019181716
RESERVEDF0PI
R-0hR-0h
15141312111098
RESERVEDF0GI
R-0hR-0h
76543210
RESERVEDF0FL
R-0hR-0h
Table 35-58 MCAN_RXF0S Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25RF0LR0hRx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset.
0 No Rx FIFO 0 message lost
1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero

Note: Overwriting the oldest message when RXF0C.F0OM = '1' will not set this flag.

Reset type: SYSRSn

24F0FR0hRx FIFO 0 Full
0 Rx FIFO 0 not full
1 Rx FIFO 0 full

Reset type: SYSRSn

23-22RESERVEDR0hReserved
21-16F0PIR0hRx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63.

Reset type: SYSRSn

15-14RESERVEDR0hReserved
13-8F0GIR0hRx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63.

Reset type: SYSRSn

7RESERVEDR0hReserved
6-0F0FLR0hRx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64.

Reset type: SYSRSn

35.7.3.28 MCAN_RXF0A Register (Offset = 54h) [Reset = 00000000h]

MCAN_RXF0A is shown in Figure 35-63 and described in Table 35-59.

Return to the Summary Table.

MCAN Rx FIFO 0 Acknowledge

Figure 35-63 MCAN_RXF0A Register
313029282726252423222120191817161514131211109876543210
RESERVEDF0AI
R-0hR/W-0h
Table 35-59 MCAN_RXF0A Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0F0AIR/W0hRx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL.

Reset type: SYSRSn

35.7.3.29 MCAN_RXBC Register (Offset = 56h) [Reset = 00000000h]

MCAN_RXBC is shown in Figure 35-64 and described in Table 35-60.

Return to the Summary Table.

MCAN Rx Buffer Configuration

Figure 35-64 MCAN_RXBC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RBSA
R/WQ-0h
76543210
RBSARESERVED
R/WQ-0hR-0h
Table 35-60 MCAN_RXBC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-2RBSAR/WQ0hRx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).

+I466

Reset type: SYSRSn

1-0RESERVEDR0hReserved

35.7.3.30 MCAN_RXF1C Register (Offset = 58h) [Reset = 00000000h]

MCAN_RXF1C is shown in Figure 35-65 and described in Table 35-61.

Return to the Summary Table.

MCAN Rx FIFO 1 Configuration

Figure 35-65 MCAN_RXF1C Register
3130292827262524
F1OMF1WM
R/WQ-0hR/WQ-0h
2322212019181716
RESERVEDF1S
R-0hR/WQ-0h
15141312111098
F1SA
R/WQ-0h
76543210
F1SARESERVED
R/WQ-0hR-0h
Table 35-61 MCAN_RXF1C Register Field Descriptions
BitFieldTypeResetDescription
31F1OMR/WQ0hFIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode.
0 FIFO 1 blocking mode
1 FIFO 1 overwrite mode

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

30-24F1WMR/WQ0hRx FIFO 1 Watermark
0 Watermark interrupt disabled
1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W)
>64 Watermark interrupt disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

23RESERVEDR0hReserved
22-16F1SR/WQ0hRx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1.
0 No Rx FIFO 1
1-64 Number of Rx FIFO 1 elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

15-2F1SAR/WQ0hRx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address).

Reset type: SYSRSn

1-0RESERVEDR0hReserved

35.7.3.31 MCAN_RXF1S Register (Offset = 5Ah) [Reset = 00000000h]

MCAN_RXF1S is shown in Figure 35-66 and described in Table 35-62.

Return to the Summary Table.

MCAN Rx FIFO 1 Status

Figure 35-66 MCAN_RXF1S Register
3130292827262524
DMSRESERVEDRF1LF1F
R-0hR-0hR-0hR-0h
2322212019181716
RESERVEDF1PI
R-0hR-0h
15141312111098
RESERVEDF1GI
R-0hR-0h
76543210
RESERVEDF1FL
R-0hR-0h
Table 35-62 MCAN_RXF1S Register Field Descriptions
BitFieldTypeResetDescription
31-30DMSR0hDebug Message Status
00 Idle state, wait for reception of debug messages, DMA request is cleared
01 Debug message A received
10 Debug messages A, B received
11 Debug messages A, B, C received, DMA request is set

Reset type: SYSRSn

29-26RESERVEDR0hReserved
25RF1LR0hRx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.
0 No Rx FIFO 1 message lost
1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero

Note: Overwriting the oldest message when RXF1C.F1OM = '1' will not set this flag.

Reset type: SYSRSn

24F1FR0hRx FIFO 1 Full
0 Rx FIFO 1 not full
1 Rx FIFO 1 full

Reset type: SYSRSn

23-22RESERVEDR0hReserved
21-16F1PIR0hRx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63.

Reset type: SYSRSn

15-14RESERVEDR0hReserved
13-8F1GIR0hRx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63.

Reset type: SYSRSn

7RESERVEDR0hReserved
6-0F1FLR0hRx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64.

Reset type: SYSRSn

35.7.3.32 MCAN_RXF1A Register (Offset = 5Ch) [Reset = 00000000h]

MCAN_RXF1A is shown in Figure 35-67 and described in Table 35-63.

Return to the Summary Table.

MCAN Rx FIFO 1 Acknowledge

Figure 35-67 MCAN_RXF1A Register
313029282726252423222120191817161514131211109876543210
RESERVEDF1AI
R-0hR/W-0h
Table 35-63 MCAN_RXF1A Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5-0F1AIR/W0hRx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL.

Reset type: SYSRSn

35.7.3.33 MCAN_RXESC Register (Offset = 5Eh) [Reset = 00000000h]

MCAN_RXESC is shown in Figure 35-68 and described in Table 35-64.

Return to the Summary Table.

Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes >8 bytes are intended for CAN FD operation only.

Figure 35-68 MCAN_RXESC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRBDS
R-0hR/WQ-0h
76543210
RESERVEDF1DSRESERVEDF0DS
R-0hR/WQ-0hR-0hR/WQ-0h
Table 35-64 MCAN_RXESC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-11RESERVEDR0hReserved
10-8RBDSR/WQ0hRx Buffer Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

7RESERVEDR0hReserved
6-4F1DSR/WQ0hRx FIFO 1 Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

3RESERVEDR0hReserved
2-0F0DSR/WQ0hRx FIFO 0 Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

35.7.3.34 MCAN_TXBC Register (Offset = 60h) [Reset = 00000000h]

MCAN_TXBC is shown in Figure 35-69 and described in Table 35-65.

Return to the Summary Table.

MCAN Tx Buffer Configuration

Figure 35-69 MCAN_TXBC Register
3130292827262524
RESERVEDTFQMTFQS
R-0hR/WQ-0hR/WQ-0h
2322212019181716
RESERVEDNDTB
R-0hR/WQ-0h
15141312111098
TBSA
R/WQ-0h
76543210
TBSARESERVED
R/WQ-0hR-0h
Table 35-65 MCAN_TXBC Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30TFQMR/WQ0hTx FIFO/Queue Mode
0 Tx FIFO operation
1 Tx Queue operation

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

29-24TFQSR/WQ0hTransmit FIFO/Queue Size
0 No Tx FIFO/Queue
1-32 Number of Tx Buffers used for Tx FIFO/Queue
>32 Values greater than 32 are interpreted as 32

Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check
for erroneous configurations. The Tx Buffers section in the Message RAM starts with the
dedicated Tx Buffers.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

23-22RESERVEDR0hReserved
21-16NDTBR/WQ0hNumber of Dedicated Transmit Buffers
0 No Dedicated Tx Buffers
1-32 Number of Dedicated Tx Buffers
>32 Values greater than 32 are interpreted as 32

Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check
for erroneous configurations. The Tx Buffers section in the Message RAM starts with the
dedicated Tx Buffers.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

15-2TBSAR/WQ0hTx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

1-0RESERVEDR0hReserved

35.7.3.35 MCAN_TXFQS Register (Offset = 62h) [Reset = 00000000h]

MCAN_TXFQS is shown in Figure 35-70 and described in Table 35-66.

Return to the Summary Table.

The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).

Figure 35-70 MCAN_TXFQS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTFQFTFQP
R-0hR-0hR-0h
15141312111098
RESERVEDTFGI
R-0hR-0h
76543210
RESERVEDTFFL
R-0hR-0h
Table 35-66 MCAN_TXFQS Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved
21TFQFR0hTx FIFO/Queue Full
0 Tx FIFO/Queue not full
1 Tx FIFO/Queue full

Reset type: SYSRSn

20-16TFQPR0hTx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer, range 0 to 31.

Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.

Reset type: SYSRSn

15-13RESERVEDR0hReserved
12-8TFGIR0hTx FIFO Get Index. Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').

Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.

Reset type: SYSRSn

7-6RESERVEDR0hReserved
5-0TFFLR0hTx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').

Reset type: SYSRSn

35.7.3.36 MCAN_TXESC Register (Offset = 64h) [Reset = 00000000h]

MCAN_TXESC is shown in Figure 35-71 and described in Table 35-67.

Return to the Summary Table.

Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only.

Figure 35-71 MCAN_TXESC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDTBDS
R-0hR/WQ-0h
Table 35-67 MCAN_TXESC Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0TBDSR/WQ0hTx Buffer Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as '0xCC' (padding bytes).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

Reset type: SYSRSn

35.7.3.37 MCAN_TXBRP Register (Offset = 66h) [Reset = 00000000h]

MCAN_TXBRP is shown in Figure 35-72 and described in Table 35-68.

Return to the Summary Table.

MCAN Tx Buffer Request Pending

Figure 35-72 MCAN_TXBRP Register
3130292827262524
TRP31TRP30TRP29TRP28TRP27TRP26TRP25TRP24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
TRP23TRP22TRP21TRP20TRP19TRP18TRP17TRP16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TRP15TRP14TRP13TRP12TRP11TRP10TRP9TRP8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TRP7TRP6TRP5TRP4TRP3TRP2TRP1TRP0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 35-68 MCAN_TXBRP Register Field Descriptions
BitFieldTypeResetDescription
31TRP31R0hTransmission Request Pending 31. See description for bit 0.

Reset type: SYSRSn

30TRP30R0hTransmission Request Pending 30. See description for bit 0.

Reset type: SYSRSn

29TRP29R0hTransmission Request Pending 29. See description for bit 0.

Reset type: SYSRSn

28TRP28R0hTransmission Request Pending 28. See description for bit 0.

Reset type: SYSRSn

27TRP27R0hTransmission Request Pending 27. See description for bit 0.

Reset type: SYSRSn

26TRP26R0hTransmission Request Pending 26. See description for bit 0.

Reset type: SYSRSn

25TRP25R0hTransmission Request Pending 25. See description for bit 0.

Reset type: SYSRSn

24TRP24R0hTransmission Request Pending 24. See description for bit 0.

Reset type: SYSRSn

23TRP23R0hTransmission Request Pending 23. See description for bit 0.

Reset type: SYSRSn

22TRP22R0hTransmission Request Pending 22. See description for bit 0.

Reset type: SYSRSn

21TRP21R0hTransmission Request Pending 21. See description for bit 0.

Reset type: SYSRSn

20TRP20R0hTransmission Request Pending 20. See description for bit 0.

Reset type: SYSRSn

19TRP19R0hTransmission Request Pending 19. See description for bit 0.

Reset type: SYSRSn

18TRP18R0hTransmission Request Pending 18. See description for bit 0.

Reset type: SYSRSn

17TRP17R0hTransmission Request Pending 17. See description for bit 0.

Reset type: SYSRSn

16TRP16R0hTransmission Request Pending 16. See description for bit 0.

Reset type: SYSRSn

15TRP15R0hTransmission Request Pending 15. See description for bit 0.

Reset type: SYSRSn

14TRP14R0hTransmission Request Pending 14. See description for bit 0.

Reset type: SYSRSn

13TRP13R0hTransmission Request Pending 13. See description for bit 0.

Reset type: SYSRSn

12TRP12R0hTransmission Request Pending 12. See description for bit 0.

Reset type: SYSRSn

11TRP11R0hTransmission Request Pending 11. See description for bit 0.

Reset type: SYSRSn

10TRP10R0hTransmission Request Pending 10. See description for bit 0.

Reset type: SYSRSn

9TRP9R0hTransmission Request Pending 9. See description for bit 0.

Reset type: SYSRSn

8TRP8R0hTransmission Request Pending 8. See description for bit 0.

Reset type: SYSRSn

7TRP7R0hTransmission Request Pending 7. See description for bit 0.

Reset type: SYSRSn

6TRP6R0hTransmission Request Pending 6. See description for bit 0.

Reset type: SYSRSn

5TRP5R0hTransmission Request Pending 5. See description for bit 0.

Reset type: SYSRSn

4TRP4R0hTransmission Request Pending 4. See description for bit 0.

Reset type: SYSRSn

3TRP3R0hTransmission Request Pending 3. See description for bit 0.

Reset type: SYSRSn

2TRP2R0hTransmission Request Pending 2. See description for bit 0.

Reset type: SYSRSn

1TRP1R0hTransmission Request Pending 1. See description for bit 0.

Reset type: SYSRSn

0TRP0R0hTransmission Request Pending 0.

Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR.

TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID).

A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset.

After a cancellation has been requested, a finished cancellation is signalled via TXBCF
- after successful transmission together with the corresponding TXBTO bit
- when the transmission has not yet been started at the point of cancellation
- when the transmission has been aborted due to lost arbitration
- when an error occurred during frame transmission

In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions.
0 No transmission request pending
1 Transmission request pending

Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset.

Reset type: SYSRSn

35.7.3.38 MCAN_TXBAR Register (Offset = 68h) [Reset = 00000000h]

MCAN_TXBAR is shown in Figure 35-73 and described in Table 35-69.

Return to the Summary Table.

MCAN Tx Buffer Add Request

Figure 35-73 MCAN_TXBAR Register
3130292827262524
AR31AR30AR29AR28AR27AR26AR25AR24
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
2322212019181716
AR23AR22AR21AR20AR19AR18AR17AR16
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
15141312111098
AR15AR14AR13AR12AR11AR10AR9AR8
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
76543210
AR7AR6AR5AR4AR3AR2AR1AR0
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
Table 35-69 MCAN_TXBAR Register Field Descriptions
BitFieldTypeResetDescription
31AR31R/WQ0hAdd Request 31. See description for bit 0.

Reset type: SYSRSn

30AR30R/WQ0hAdd Request 30. See description for bit 0.

Reset type: SYSRSn

29AR29R/WQ0hAdd Request 29. See description for bit 0.

Reset type: SYSRSn

28AR28R/WQ0hAdd Request 28. See description for bit 0.

Reset type: SYSRSn

27AR27R/WQ0hAdd Request 27. See description for bit 0.

Reset type: SYSRSn

26AR26R/WQ0hAdd Request 26. See description for bit 0.

Reset type: SYSRSn

25AR25R/WQ0hAdd Request 25. See description for bit 0.

Reset type: SYSRSn

24AR24R/WQ0hAdd Request 24. See description for bit 0.

Reset type: SYSRSn

23AR23R/WQ0hAdd Request 23. See description for bit 0.

Reset type: SYSRSn

22AR22R/WQ0hAdd Request 22. See description for bit 0.

Reset type: SYSRSn

21AR21R/WQ0hAdd Request 21. See description for bit 0.

Reset type: SYSRSn

20AR20R/WQ0hAdd Request 20. See description for bit 0.

Reset type: SYSRSn

19AR19R/WQ0hAdd Request 19. See description for bit 0.

Reset type: SYSRSn

18AR18R/WQ0hAdd Request 18. See description for bit 0.

Reset type: SYSRSn

17AR17R/WQ0hAdd Request 17. See description for bit 0.

Reset type: SYSRSn

16AR16R/WQ0hAdd Request 16. See description for bit 0.

Reset type: SYSRSn

15AR15R/WQ0hAdd Request 15. See description for bit 0.

Reset type: SYSRSn

14AR14R/WQ0hAdd Request 14. See description for bit 0.

Reset type: SYSRSn

13AR13R/WQ0hAdd Request 13. See description for bit 0.

Reset type: SYSRSn

12AR12R/WQ0hAdd Request 12. See description for bit 0.

Reset type: SYSRSn

11AR11R/WQ0hAdd Request 11. See description for bit 0.

Reset type: SYSRSn

10AR10R/WQ0hAdd Request 10. See description for bit 0.

Reset type: SYSRSn

9AR9R/WQ0hAdd Request 9. See description for bit 0.

Reset type: SYSRSn

8AR8R/WQ0hAdd Request 8. See description for bit 0.

Reset type: SYSRSn

7AR7R/WQ0hAdd Request 7. See description for bit 0.

Reset type: SYSRSn

6AR6R/WQ0hAdd Request 6. See description for bit 0.

Reset type: SYSRSn

5AR5R/WQ0hAdd Request 5. See description for bit 0.

Reset type: SYSRSn

4AR4R/WQ0hAdd Request 4. See description for bit 0.

Reset type: SYSRSn

3AR3R/WQ0hAdd Request 3. See description for bit 0.

Reset type: SYSRSn

2AR2R/WQ0hAdd Request 2. See description for bit 0.

Reset type: SYSRSn

1AR1R/WQ0hAdd Request 1. See description for bit 0.

Reset type: SYSRSn

0AR0R/WQ0hAdd Request 0.

Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit
writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed.
0 No transmission request added
1 Transmission requested added

Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored.

Qualified Write is possible only with CCCR.CCE='0'

Reset type: SYSRSn

35.7.3.39 MCAN_TXBCR Register (Offset = 6Ah) [Reset = 00000000h]

MCAN_TXBCR is shown in Figure 35-74 and described in Table 35-70.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Request

Figure 35-74 MCAN_TXBCR Register
3130292827262524
CR31CR30CR29CR28CR27CR26CR25CR24
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
2322212019181716
CR23CR22CR21CR20CR19CR18CR17CR16
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
15141312111098
CR15CR14CR13CR12CR11CR10CR9CR8
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
76543210
CR7CR6CR5CR4CR3CR2CR1CR0
R/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0hR/WQ-0h
Table 35-70 MCAN_TXBCR Register Field Descriptions
BitFieldTypeResetDescription
31CR31R/WQ0hCancellation Request 31. See description for bit 0.

Reset type: SYSRSn

30CR30R/WQ0hCancellation Request 30. See description for bit 0.

Reset type: SYSRSn

29CR29R/WQ0hCancellation Request 29. See description for bit 0.

Reset type: SYSRSn

28CR28R/WQ0hCancellation Request 28. See description for bit 0.

Reset type: SYSRSn

27CR27R/WQ0hCancellation Request 27. See description for bit 0.

Reset type: SYSRSn

26CR26R/WQ0hCancellation Request 26. See description for bit 0.

Reset type: SYSRSn

25CR25R/WQ0hCancellation Request 25. See description for bit 0.

Reset type: SYSRSn

24CR24R/WQ0hCancellation Request 24. See description for bit 0.

Reset type: SYSRSn

23CR23R/WQ0hCancellation Request 23. See description for bit 0.

Reset type: SYSRSn

22CR22R/WQ0hCancellation Request 22. See description for bit 0.

Reset type: SYSRSn

21CR21R/WQ0hCancellation Request 21. See description for bit 0.

Reset type: SYSRSn

20CR20R/WQ0hCancellation Request 20. See description for bit 0.

Reset type: SYSRSn

19CR19R/WQ0hCancellation Request 19. See description for bit 0.

Reset type: SYSRSn

18CR18R/WQ0hCancellation Request 18. See description for bit 0.

Reset type: SYSRSn

17CR17R/WQ0hCancellation Request 17. See description for bit 0.

Reset type: SYSRSn

16CR16R/WQ0hCancellation Request 16. See description for bit 0.

Reset type: SYSRSn

15CR15R/WQ0hCancellation Request 15. See description for bit 0.

Reset type: SYSRSn

14CR14R/WQ0hCancellation Request 14. See description for bit 0.

Reset type: SYSRSn

13CR13R/WQ0hCancellation Request 13. See description for bit 0.

Reset type: SYSRSn

12CR12R/WQ0hCancellation Request 12. See description for bit 0.

Reset type: SYSRSn

11CR11R/WQ0hCancellation Request 11. See description for bit 0.

Reset type: SYSRSn

10CR10R/WQ0hCancellation Request 10. See description for bit 0.

Reset type: SYSRSn

9CR9R/WQ0hCancellation Request 9. See description for bit 0.

Reset type: SYSRSn

8CR8R/WQ0hCancellation Request 8. See description for bit 0.

Reset type: SYSRSn

7CR7R/WQ0hCancellation Request 7. See description for bit 0.

Reset type: SYSRSn

6CR6R/WQ0hCancellation Request 6. See description for bit 0.

Reset type: SYSRSn

5CR5R/WQ0hCancellation Request 5. See description for bit 0.

Reset type: SYSRSn

4CR4R/WQ0hCancellation Request 4. See description for bit 0.

Reset type: SYSRSn

3CR3R/WQ0hCancellation Request 3. See description for bit 0.

Reset type: SYSRSn

2CR2R/WQ0hCancellation Request 2. See description for bit 0.

Reset type: SYSRSn

1CR1R/WQ0hCancellation Request 1. See description for bit 0.

Reset type: SYSRSn

0CR0R/WQ0hCancellation Request 0.

Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit
writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset.
0 No cancellation pending
1 Cancellation pending

Qualified Write is possible only with CCCR.CCE='0'

Reset type: SYSRSn

35.7.3.40 MCAN_TXBTO Register (Offset = 6Ch) [Reset = 00000000h]

MCAN_TXBTO is shown in Figure 35-75 and described in Table 35-71.

Return to the Summary Table.

MCAN Tx Buffer Transmission Occurred

Figure 35-75 MCAN_TXBTO Register
3130292827262524
TO31TO30TO29TO28TO27TO26TO25TO24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
TO23TO22TO21TO20TO19TO18TO17TO16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TO15TO14TO13TO12TO11TO10TO9TO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TO7TO6TO5TO4TO3TO2TO1TO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 35-71 MCAN_TXBTO Register Field Descriptions
BitFieldTypeResetDescription
31TO31R0hTransmission Occurred 31. See description for bit 0.

Reset type: SYSRSn

30TO30R0hTransmission Occurred 30. See description for bit 0.

Reset type: SYSRSn

29TO29R0hTransmission Occurred 29. See description for bit 0.

Reset type: SYSRSn

28TO28R0hTransmission Occurred 28. See description for bit 0.

Reset type: SYSRSn

27TO27R0hTransmission Occurred 27. See description for bit 0.

Reset type: SYSRSn

26TO26R0hTransmission Occurred 26. See description for bit 0.

Reset type: SYSRSn

25TO25R0hTransmission Occurred 25. See description for bit 0.

Reset type: SYSRSn

24TO24R0hTransmission Occurred 24. See description for bit 0.

Reset type: SYSRSn

23TO23R0hTransmission Occurred 23. See description for bit 0.

Reset type: SYSRSn

22TO22R0hTransmission Occurred 22. See description for bit 0.

Reset type: SYSRSn

21TO21R0hTransmission Occurred 21. See description for bit 0.

Reset type: SYSRSn

20TO20R0hTransmission Occurred 20. See description for bit 0.

Reset type: SYSRSn

19TO19R0hTransmission Occurred 19. See description for bit 0.

Reset type: SYSRSn

18TO18R0hTransmission Occurred 18. See description for bit 0.

Reset type: SYSRSn

17TO17R0hTransmission Occurred 17. See description for bit 0.

Reset type: SYSRSn

16TO16R0hTransmission Occurred 16. See description for bit 0.

Reset type: SYSRSn

15TO15R0hTransmission Occurred 15. See description for bit 0.

Reset type: SYSRSn

14TO14R0hTransmission Occurred 14. See description for bit 0.

Reset type: SYSRSn

13TO13R0hTransmission Occurred 13. See description for bit 0.

Reset type: SYSRSn

12TO12R0hTransmission Occurred 12. See description for bit 0.

Reset type: SYSRSn

11TO11R0hTransmission Occurred 11. See description for bit 0.

Reset type: SYSRSn

10TO10R0hTransmission Occurred 10. See description for bit 0.

Reset type: SYSRSn

9TO9R0hTransmission Occurred 9. See description for bit 0.

Reset type: SYSRSn

8TO8R0hTransmission Occurred 8. See description for bit 0.

Reset type: SYSRSn

7TO7R0hTransmission Occurred 7. See description for bit 0.

Reset type: SYSRSn

6TO6R0hTransmission Occurred 6. See description for bit 0.

Reset type: SYSRSn

5TO5R0hTransmission Occurred 5. See description for bit 0.

Reset type: SYSRSn

4TO4R0hTransmission Occurred 4. See description for bit 0.

Reset type: SYSRSn

3TO3R0hTransmission Occurred 3. See description for bit 0.

Reset type: SYSRSn

2TO2R0hTransmission Occurred 2. See description for bit 0.

Reset type: SYSRSn

1TO1R0hTransmission Occurred 1. See description for bit 0.

Reset type: SYSRSn

0TO0R0hTransmission Occurred 0.

Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.
0 No transmission occurred
1 Transmission occurred

Reset type: SYSRSn

35.7.3.41 MCAN_TXBCF Register (Offset = 6Eh) [Reset = 00000000h]

MCAN_TXBCF is shown in Figure 35-76 and described in Table 35-72.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Finished

Figure 35-76 MCAN_TXBCF Register
3130292827262524
CF31CF30CF29CF28CF27CF26CF25CF24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
CF23CF22CF21CF20CF19CF18CF17CF16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
CF15CF14CF13CF12CF11CF10CF9CF8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CF7CF6CF5CF4CF3CF2CF1CF0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 35-72 MCAN_TXBCF Register Field Descriptions
BitFieldTypeResetDescription
31CF31R0hCancellation Finished 31. See description for bit 0.

Reset type: SYSRSn

30CF30R0hCancellation Finished 30. See description for bit 0.

Reset type: SYSRSn

29CF29R0hCancellation Finished 29. See description for bit 0.

Reset type: SYSRSn

28CF28R0hCancellation Finished 28. See description for bit 0.

Reset type: SYSRSn

27CF27R0hCancellation Finished 27. See description for bit 0.

Reset type: SYSRSn

26CF26R0hCancellation Finished 26. See description for bit 0.

Reset type: SYSRSn

25CF25R0hCancellation Finished 25. See description for bit 0.

Reset type: SYSRSn

24CF24R0hCancellation Finished 24. See description for bit 0.

Reset type: SYSRSn

23CF23R0hCancellation Finished 23. See description for bit 0.

Reset type: SYSRSn

22CF22R0hCancellation Finished 22. See description for bit 0.

Reset type: SYSRSn

21CF21R0hCancellation Finished 21. See description for bit 0.

Reset type: SYSRSn

20CF20R0hCancellation Finished 20. See description for bit 0.

Reset type: SYSRSn

19CF19R0hCancellation Finished 19. See description for bit 0.

Reset type: SYSRSn

18CF18R0hCancellation Finished 18. See description for bit 0.

Reset type: SYSRSn

17CF17R0hCancellation Finished 17. See description for bit 0.

Reset type: SYSRSn

16CF16R0hCancellation Finished 16. See description for bit 0.

Reset type: SYSRSn

15CF15R0hCancellation Finished 15. See description for bit 0.

Reset type: SYSRSn

14CF14R0hCancellation Finished 14. See description for bit 0.

Reset type: SYSRSn

13CF13R0hCancellation Finished 13. See description for bit 0.

Reset type: SYSRSn

12CF12R0hCancellation Finished 12. See description for bit 0.

Reset type: SYSRSn

11CF11R0hCancellation Finished 11. See description for bit 0.

Reset type: SYSRSn

10CF10R0hCancellation Finished 10. See description for bit 0.

Reset type: SYSRSn

9CF9R0hCancellation Finished 9. See description for bit 0.

Reset type: SYSRSn

8CF8R0hCancellation Finished 8. See description for bit 0.

Reset type: SYSRSn

7CF7R0hCancellation Finished 7. See description for bit 0.

Reset type: SYSRSn

6CF6R0hCancellation Finished 6. See description for bit 0.

Reset type: SYSRSn

5CF5R0hCancellation Finished 5. See description for bit 0.

Reset type: SYSRSn

4CF4R0hCancellation Finished 4. See description for bit 0.

Reset type: SYSRSn

3CF3R0hCancellation Finished 3. See description for bit 0.

Reset type: SYSRSn

2CF2R0hCancellation Finished 2. See description for bit 0.

Reset type: SYSRSn

1CF1R0hCancellation Finished 1. See description for bit 0.

Reset type: SYSRSn

0CF0R0hCancellation Finished 0.

Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.
0 No transmit buffer cancellation
1 Transmit buffer cancellation finished

Reset type: SYSRSn

35.7.3.42 MCAN_TXBTIE Register (Offset = 70h) [Reset = 00000000h]

MCAN_TXBTIE is shown in Figure 35-77 and described in Table 35-73.

Return to the Summary Table.

MCAN Tx Buffer Transmission Interrupt Enable

Figure 35-77 MCAN_TXBTIE Register
3130292827262524
TIE31TIE30TIE29TIE28TIE27TIE26TIE25TIE24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
TIE23TIE22TIE21TIE20TIE19TIE18TIE17TIE16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TIE15TIE14TIE13TIE12TIE11TIE10TIE9TIE8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TIE7TIE6TIE5TIE4TIE3TIE2TIE1TIE0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 35-73 MCAN_TXBTIE Register Field Descriptions
BitFieldTypeResetDescription
31TIE31R/W0hTransmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

30TIE30R/W0hTransmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

29TIE29R/W0hTransmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

28TIE28R/W0hTransmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

27TIE27R/W0hTransmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

26TIE26R/W0hTransmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

25TIE25R/W0hTransmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

24TIE24R/W0hTransmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

23TIE23R/W0hTransmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

22TIE22R/W0hTransmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

21TIE21R/W0hTransmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

20TIE20R/W0hTransmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

19TIE19R/W0hTransmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

18TIE18R/W0hTransmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

17TIE17R/W0hTransmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

16TIE16R/W0hTransmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

15TIE15R/W0hTransmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

14TIE14R/W0hTransmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

13TIE13R/W0hTransmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

12TIE12R/W0hTransmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

11TIE11R/W0hTransmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

10TIE10R/W0hTransmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

9TIE9R/W0hTransmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

8TIE8R/W0hTransmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

7TIE7R/W0hTransmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

6TIE6R/W0hTransmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

5TIE5R/W0hTransmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

4TIE4R/W0hTransmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

3TIE3R/W0hTransmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

2TIE2R/W0hTransmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

1TIE1R/W0hTransmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

0TIE0R/W0hTransmission Interrupt Enable 0.
0 Transmission interrupt disabled
1 Transmission interrupt enable

Reset type: SYSRSn

35.7.3.43 MCAN_TXBCIE Register (Offset = 72h) [Reset = 00000000h]

MCAN_TXBCIE is shown in Figure 35-78 and described in Table 35-74.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Finished Interrupt Enable

Figure 35-78 MCAN_TXBCIE Register
3130292827262524
CFIE31CFIE30CFIE29CFIE28CFIE27CFIE26CFIE25CFIE24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CFIE23CFIE22CFIE21CFIE20CFIE19CFIE18CFIE17CFIE16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CFIE15CFIE14CFIE13CFIE12CFIE11CFIE10CFIE9CFIE8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CFIE7CFIE6CFIE5CFIE4CFIE3CFIE2CFIE1CFIE0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 35-74 MCAN_TXBCIE Register Field Descriptions
BitFieldTypeResetDescription
31CFIE31R/W0hCancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

30CFIE30R/W0hCancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

29CFIE29R/W0hCancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

28CFIE28R/W0hCancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

27CFIE27R/W0hCancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

26CFIE26R/W0hCancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

25CFIE25R/W0hCancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

24CFIE24R/W0hCancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

23CFIE23R/W0hCancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

22CFIE22R/W0hCancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

21CFIE21R/W0hCancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

20CFIE20R/W0hCancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

19CFIE19R/W0hCancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

18CFIE18R/W0hCancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

17CFIE17R/W0hCancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

16CFIE16R/W0hCancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

15CFIE15R/W0hCancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

14CFIE14R/W0hCancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

13CFIE13R/W0hCancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

12CFIE12R/W0hCancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

11CFIE11R/W0hCancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

10CFIE10R/W0hCancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

9CFIE9R/W0hCancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

8CFIE8R/W0hCancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

7CFIE7R/W0hCancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

6CFIE6R/W0hCancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

5CFIE5R/W0hCancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

4CFIE4R/W0hCancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

3CFIE3R/W0hCancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

2CFIE2R/W0hCancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

1CFIE1R/W0hCancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

0CFIE0R/W0hCancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

Reset type: SYSRSn

35.7.3.44 MCAN_TXEFC Register (Offset = 78h) [Reset = 00000000h]

MCAN_TXEFC is shown in Figure 35-79 and described in Table 35-75.

Return to the Summary Table.

MCAN Tx Event FIFO Configuration

Figure 35-79 MCAN_TXEFC Register
3130292827262524
RESERVEDEFWM
R-0hR/WQ-0h
2322212019181716
RESERVEDEFS
R-0hR/WQ-0h
15141312111098
EFSA
R/WQ-0h
76543210
EFSARESERVED
R/WQ-0hR-0h
Table 35-75 MCAN_TXEFC Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-24EFWMR/WQ0hEvent FIFO Watermark
0 Watermark interrupt disabled
1-32 Level for Tx Event FIFO watermark interrupt (IR.TEFW)
>32 Watermark interrupt disabled

Reset type: SYSRSn

23-22RESERVEDR0hReserved
21-16EFSR/WQ0hEvent FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1.
0 Tx Event FIFO disabled
1-32 Number of Tx Event FIFO elements
>32 Values greater than 32 are interpreted as 32

Reset type: SYSRSn

15-2EFSAR/WQ0hEvent FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address).

Reset type: SYSRSn

1-0RESERVEDR0hReserved

35.7.3.45 MCAN_TXEFS Register (Offset = 7Ah) [Reset = 00000000h]

MCAN_TXEFS is shown in Figure 35-80 and described in Table 35-76.

Return to the Summary Table.

MCAN Tx Event FIFO Status

Figure 35-80 MCAN_TXEFS Register
3130292827262524
RESERVEDTEFLEFF
R-0hR-0hR-0h
2322212019181716
RESERVEDEFPI
R-0hR-0h
15141312111098
RESERVEDEFGI
R-0hR-0h
76543210
RESERVEDEFFL
R-0hR-0h
Table 35-76 MCAN_TXEFS Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25TEFLR0hTx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset.
0 No Tx Event FIFO element lost
1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.

Reset type: SYSRSn

24EFFR0hEvent FIFO Full
0 Tx Event FIFO not full
1 Tx Event FIFO full

Reset type: SYSRSn

23-21RESERVEDR0hReserved
20-16EFPIR0hEvent FIFO Put Index.Tx Event FIFO write index pointer, range 0 to 31.

Reset type: SYSRSn

15-13RESERVEDR0hReserved
12-8EFGIR0hEvent FIFO Get Index. Tx Event FIFO read index pointer, range 0 to 31.

Reset type: SYSRSn

7-6RESERVEDR0hReserved
5-0EFFLR0hEvent FIFO Fill Level. Number of elements stored in Tx Event FIFO, range 0 to 32.

Reset type: SYSRSn

35.7.3.46 MCAN_TXEFA Register (Offset = 7Ch) [Reset = 00000000h]

MCAN_TXEFA is shown in Figure 35-81 and described in Table 35-77.

Return to the Summary Table.

MCAN Tx Event FIFO Acknowledge

Figure 35-81 MCAN_TXEFA Register
313029282726252423222120191817161514131211109876543210
RESERVEDEFAI
R-0hR/W-0h
Table 35-77 MCAN_TXEFA Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-0EFAIR/W0hEvent FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL.

Reset type: SYSRSn