SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
FSI is a point-to-point communication protocol. Hence, an FSI transmitter core communicates directly to a single FSI receiver core. Similarly, an FSI receiver core receives data from a single FSI transmitter core.
Each FSI core has three signals: one clock and two data signals. Data is always transmitted or received with the most-significant bit of each frame field being first. If multilane transmissions are not used, the TXD1 and RXD1 signals can be left unconnected and the GPIOs repurposed for other application needs. Table 27-1 and Table 27-2 describe the various signals that can be selected by the PADCONFIG register to be brought out to device pins.
Signal Name | Direction | Description | Inactive Level(1) |
---|---|---|---|
RXCLK | Input | This is the receive clock input signal for the FSI receive module. | Logic High |
This must be connected to TXCLK of the transmitting FSI module. | |||
RXD0 | Input | This is the primary data input line for reception. This must be connected to the TXD0 of the transmitting FSI module. | Logic High |
RXD1 | Input | This is an additional data input line for reception. This signal must be connected to the TXD1 of the transmitting FSI module to use multilane transmission. | Logic High |
Signal Name | Direction | Description | Inactive Level(1) |
---|---|---|---|
TXCLK | Output | This is the transmit clock and is driven by the FSI transmit module. | Logic High |
During a transmission, four clock edges are transmitted before the start of frame phase (preamble) and four clock edges follow the last bit of the frame (postamble). Data is transmitted on both edges of the clock. | |||
In FSI-SPI compatibility mode, the preamble and the post frame clock edges are not transmitted. Data is transmitted only on one edge of the clock. Data transmits on rising edge and received on falling edge of the clock. | |||
TXD0 | Output | This is the primary data output line for transmission and is driven by the FSI transmit module. | Logic High |
When the FSI is configured for multilane transmission, TXD0 contains all the even numbered bits of the data and CRC bytes. Other frame fields such as frame type, start-of-frame, tag, and end-of-frame are transmitted in full. | |||
TXD1 | Output | This is an additional data output line for transmission, if the FSI is configured for multilane transmission. This signal is driven by the FSI transmit module. | Logic High |
During transmission, the data bits are split between TXD0 and TXD1. TXD1 contains all the odd numbered bits of the data and CRC bytes. This applies only to the data words and the CRC bytes. Other data frame related information like Frame Type, Start-of-Frame, Tag and End-of-frame, the state of this line are identical to TXD0. |