SPRUIZ1 User guide

SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

1
Read This First
1. About This Manual
2. Notational Conventions
3. Glossary
4. Related Documentation From Texas Instruments
5. Support Resources
6. Trademarks
1 C2000™ Microcontrollers Software Support
1. 1.1 Introduction
2. 1.2 C2000Ware Structure
3. 1.3 Documentation
4. 1.4 Devices
5. 1.5 Libraries
6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
7. 1.7 SysConfig and PinMUX Tool
2 C28x Processor
1. 2.1 Introduction
2. 2.2 C28X Related Collateral
3. 2.3 Features
4. 2.4 Floating-Point Unit (FPU)
5. 2.5 Trigonometric Math Unit (TMU)
6. 2.6 VCRC Unit
3 C28x System Control and Interrupts
1. 3.1 C28x System Control Introduction
  1. 3.1.1 SYSCTL Related Collateral
2. 3.2 System Control Functional Description
  1. 3.2.1 Device Identification
3. 3.3 Resets
4. 3.4 Peripheral Interrupts
5. 3.5 Exceptions and Non-Maskable Interrupts
6. 3.6 Safety Features
7. 3.7 Clocking
8. 3.8 Clock Configuration Semaphore
9. 3.9 32-Bit CPU Timers 0/1/2
10. 3.10 Watchdog Timers
11. 3.11 Low-Power Modes
12. 3.12 Memory Controller Module
13. 3.13 JTAG
  1. 3.13.1 JTAG Noise and TAP_STATUS
14. 3.14 Live Firmware Update (LFU)
15. 3.15 System Control Register Configuration Restrictions
16. 3.16 MCU Configuration (MCUCNFx)
17. 3.17 Software
18. 3.18 System Control Registers
4 ROM Code and Peripheral Booting
1. 4.1 Introduction
  1. 4.1.1 ROM Related Collateral
2. 4.2 Device Boot Sequence
3. 4.3 Device Boot Modes
  1. 4.3.1 Default Boot Modes
  2. 4.3.2 Custom Boot Modes
4. 4.4 Device Boot Configurations
5. 4.5 Device Boot Flow Diagrams
6. 4.6 Device Reset and Exception Handling
  1. 4.6.1 Reset Causes and Handling
  2. 4.6.2 Exceptions and Interrupts Handling
7. 4.7 Boot ROM Description
8. 4.8 Application Notes for Using the Bootloaders
  1. 4.8.1 Bootloader Data Stream Structure
    1. 4.8.1.1 Data Stream Structure 8-bit
  2. 4.8.2 The C2000 Hex Utility
    1. 4.8.2.1 HEX2000.exe Command Syntax
9. 4.9 Software
  1. 4.9.1 BOOT Examples
5 Dual Code Security Module (DCSM)
1. 5.1 Introduction
  1. 5.1.1 DCSM Related Collateral
2. 5.2 Functional Description
3. 5.3 Flash and OTP Erase/Program
4. 5.4 Secure Copy Code
5. 5.5 SecureCRC
6. 5.6 CSM Impact on Other On-Chip Resources
  1. 5.6.1 RAMOPEN
7. 5.7 Incorporating Code Security in User Applications
8. 5.8 Software
  1. 5.8.1 DCSM Examples
    1. 5.8.1.1 Empty DCSM Tool Example
    2. 5.8.1.2 DCSM Memory partitioning Example
9. 5.9 DCSM Registers
6 Background CRC-32 (BGCRC)
1. 6.1 Introduction
2. 6.2 Functional Description
3. 6.3 Application of the BGCRC
4. 6.4 Software
  1. 6.4.1 BGCRC Examples
5. 6.5 BGCRC Registers
7 Control Law Accelerator (CLA)
1. 7.1 Introduction
2. 7.2 CLA Interface
3. 7.3 CLA, DMA, and CPU Arbitration
4. 7.4 CLA Configuration and Debug
5. 7.5 Pipeline
6. 7.6 Software
  1. 7.6.1 CLA Examples
7. 7.7 Instruction Set
  1. 7.7.1 Instruction Descriptions
  2. 7.7.2 Addressing Modes and Encoding
  3. 7.7.3 Instructions
    1. MABSF32 MRa, MRb
    2. MADD32 MRa, MRb, MRc
    3. MADDF32 MRa, #16FHi, MRb
    4. MADDF32 MRa, MRb, #16FHi
    5. MADDF32 MRa, MRb, MRc
    6. MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
    7. MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    8. MAND32 MRa, MRb, MRc
    9. MASR32 MRa, #SHIFT
    10. MBCNDD 16BitDest [, CNDF]
    11. MCCNDD 16BitDest [, CNDF]
    12. MCLRC BGINTM
    13. MCMP32 MRa, MRb
    14. MCMPF32 MRa, MRb
    15. MCMPF32 MRa, #16FHi
    16. MDEBUGSTOP
    17. MDEBUGSTOP1
    18. MEALLOW
    19. MEDIS
    20. MEINVF32 MRa, MRb
    21. MEISQRTF32 MRa, MRb
    22. MF32TOI16 MRa, MRb
    23. MF32TOI16R MRa, MRb
    24. MF32TOI32 MRa, MRb
    25. MF32TOUI16 MRa, MRb
    26. MF32TOUI16R MRa, MRb
    27. MF32TOUI32 MRa, MRb
    28. MFRACF32 MRa, MRb
    29. MI16TOF32 MRa, MRb
    30. MI16TOF32 MRa, mem16
    31. MI32TOF32 MRa, mem32
    32. MI32TOF32 MRa, MRb
    33. MLSL32 MRa, #SHIFT
    34. MLSR32 MRa, #SHIFT
    35. MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
    36. MMAXF32 MRa, MRb
    37. MMAXF32 MRa, #16FHi
    38. MMINF32 MRa, MRb
    39. MMINF32 MRa, #16FHi
    40. MMOV16 MARx, MRa, #16I
    41. MMOV16 MARx, mem16
    42. MMOV16 mem16, MARx
    43. MMOV16 mem16, MRa
    44. MMOV32 mem32, MRa
    45. MMOV32 mem32, MSTF
    46. MMOV32 MRa, mem32 [, CNDF]
    47. MMOV32 MRa, MRb [, CNDF]
    48. MMOV32 MSTF, mem32
    49. MMOVD32 MRa, mem32
    50. MMOVF32 MRa, #32F
    51. MMOVI16 MARx, #16I
    52. MMOVI32 MRa, #32FHex
    53. MMOVIZ MRa, #16FHi
    54. MMOVZ16 MRa, mem16
    55. MMOVXI MRa, #16FLoHex
    56. MMPYF32 MRa, MRb, MRc
    57. MMPYF32 MRa, #16FHi, MRb
    58. MMPYF32 MRa, MRb, #16FHi
    59. MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
    60. MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    61. MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
    62. MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
    63. MNEGF32 MRa, MRb[, CNDF]
    64. MNOP
    65. MOR32 MRa, MRb, MRc
    66. MRCNDD [CNDF]
    67. MSETC BGINTM
    68. MSETFLG FLAG, VALUE
    69. MSTOP
    70. MSUB32 MRa, MRb, MRc
    71. MSUBF32 MRa, MRb, MRc
    72. MSUBF32 MRa, #16FHi, MRb
    73. MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    74. MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
    75. MSWAPF MRa, MRb [, CNDF]
    76. MTESTTF CNDF
    77. MUI16TOF32 MRa, mem16
    78. MUI16TOF32 MRa, MRb
    79. MUI32TOF32 MRa, mem32
    80. MUI32TOF32 MRa, MRb
    81. MXOR32 MRa, MRb, MRc
8. 7.8 CLA Registers
8 Configurable Logic Block (CLB)
1. 8.1 Introduction
  1. 8.1.1 CLB Related Collateral
2. 8.2 Description
  1. 8.2.1 CLB Clock
3. 8.3 CLB Input/Output Connection
4. 8.4 CLB Tile
5. 8.5 CPU Interface
  1. 8.5.1 Register Description
  2. 8.5.2 Non-Memory Mapped Registers
6. 8.6 DMA Access
7. 8.7 CLB Data Export Through SPI RX Buffer
8. 8.8 CLB Pipeline Mode
9. 8.9 Software
  1. 8.9.1 CLB Examples
10. 8.10 CLB Registers
9 Dual-Clock Comparator (DCC)
1. 9.1 Introduction
  1. 9.1.1 Features
  2. 9.1.2 Block Diagram
2. 9.2 Module Operation
3. 9.3 Interrupts
4. 9.4 Software
  1. 9.4.1 DCC Examples
5. 9.5 DCC Registers
10Direct Memory Access (DMA)
1. 10.1 Introduction
  1. 10.1.1 Features
  2. 10.1.2 Block Diagram
2. 10.2 Architecture
  1. 10.2.1 Peripheral Interrupt Event Trigger Sources
  2. 10.2.2 DMA Bus
3. 10.3 Address Pointer and Transfer Control
4. 10.4 Pipeline Timing and Throughput
5. 10.5 CPU and CLA Arbitration
6. 10.6 Channel Priority
  1. 10.6.1 Round-Robin Mode
  2. 10.6.2 Channel 1 High-Priority Mode
7. 10.7 Overrun Detection Feature
8. 10.8 Software
  1. 10.8.1 DMA Examples
9. 10.9 DMA Registers
11External Memory Interface (EMIF)
1. 11.1 Introduction
2. 11.2 EMIF Module Architecture
3. 11.3 Example Configuration
  1. 11.3.1 Hardware Interface
  2. 11.3.2 Software Configuration
    1. 11.3.2.1 Configuring the SDRAM Interface
    2. 11.3.2.2 Configuring the Flash Interface
      1. 11.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
4. 11.4 Software
  1. 11.4.1 EMIF Examples
5. 11.5 EMIF Registers
12Flash Module
1. 12.1 Introduction to Flash and OTP Memory
2. 12.2 Flash Bank, OTP, and Pump
3. 12.3 Flash Wrapper
4. 12.4 Flash and OTP Memory Performance
5. 12.5 Flash Read Interface
  1. 12.5.1 C28x-Flash Read Interface
6. 12.6 Flash Erase and Program
7. 12.7 Error Correction Code (ECC) Protection
8. 12.8 Reserved Locations Within Flash and OTP
9. 12.9 Migrating an Application from RAM to Flash
10. 12.10 Procedure to Change the Flash Control Registers
11. 12.11 Software
  1. 12.11.1 FLASH Examples
12. 12.12 Flash Registers
13Embedded Real-time Analysis and Diagnostic (ERAD)
1. 13.1 Introduction
  1. 13.1.1 ERAD Related Collateral
2. 13.2 Enhanced Bus Comparator Unit
  1. 13.2.1 Enhanced Bus Comparator Unit Operations
  2. 13.2.2 Event Masking and Exporting
3. 13.3 System Event Counter Unit
4. 13.4 ERAD Ownership, Initialization and Reset
5. 13.5 ERAD Programming Sequence
  1. 13.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
  2. 13.5.2 Timer and Counter Programming Sequence
6. 13.6 Cyclic Redundancy Check Unit
  1. 13.6.1 CRC Unit Qualifier
  2. 13.6.2 CRC Unit Programming Sequence
7. 13.7 Program Counter Trace
8. 13.8 Software
  1. 13.8.1 ERAD Examples
9. 13.9 ERAD Registers
14General-Purpose Input/Output (GPIO)
1. 14.1 Introduction
  1. 14.1.1 GPIO Related Collateral
2. 14.2 Configuration Overview
3. 14.3 Digital Inputs on ADC Pins (AIOs)
4. 14.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
5. 14.5 Digital General-Purpose I/O Control
6. 14.6 Input Qualification
7. 14.7 USB Signals
8. 14.8 GPIO and Peripheral Muxing
  1. 14.8.1 GPIO Muxing
  2. 14.8.2 Peripheral Muxing
9. 14.9 Internal Pullup Configuration Requirements
10. 14.10 Software
  1. 14.10.1 GPIO Examples
    1. 14.10.1.1 Device GPIO Toggle - SINGLE_CORE
    2. 14.10.1.2 XINT/XBAR example - SINGLE_CORE
  2. 14.10.2 LED Examples
11. 14.11 GPIO Registers
15Interprocessor Communication (IPC)
1. 15.1 Introduction
2. 15.2 Message RAMs
3. 15.3 IPC Flags and Interrupts
4. 15.4 IPC Command Registers
5. 15.5 Free-Running Counter
6. 15.6 IPC Communication Protocol
7. 15.7 Software
  1. 15.7.1 IPC Examples
8. 15.8 IPC Registers
16Crossbar (X-BAR)
1. 16.1 Input X-BAR, ICL XBAR, MINDB XBAR, and CLB Input X-BAR
  1. 16.1.1 CLB Input X-BAR
  2. 16.1.2 ICL and MINDB X-BAR
2. 16.2 ePWM , CLB, and GPIO Output X-BAR
3. 16.3 XBAR Registers
17Analog Subsystem
1. 17.1 Introduction
  1. 17.1.1 Features
  2. 17.1.2 Block Diagram
2. 17.2 Optimizing Power-Up Time
3. 17.3 Digital Inputs on ADC Pins (AIOs)
4. 17.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
5. 17.5 Analog Subsystem Registers
  1. 17.5.1 ASBSYS Base Address Table
  2. 17.5.2 ANALOG_SUBSYS_REGS Registers
18Analog-to-Digital Converter (ADC)
1. 18.1 Introduction
2. 18.2 ADC Configurability
3. 18.3 SOC Principle of Operation
4. 18.4 SOC Configuration Examples
5. 18.5 ADC Conversion Priority
6. 18.6 Burst Mode
  1. 18.6.1 Burst Mode Example
  2. 18.6.2 Burst Mode Priority Example
7. 18.7 EOC and Interrupt Operation
8. 18.8 Post-Processing Blocks
9. 18.9 Result Safety Checker
  1. 18.9.1 Result Safety Checker Operation
  2. 18.9.2 Result Safety Checker Interrupts and Events
10. 18.10 Opens/Shorts Detection Circuit (OSDETECT)
11. 18.11 Power-Up Sequence
12. 18.12 ADC Calibration
  1. 18.12.1 ADC Zero Offset Calibration
13. 18.13 ADC Timings
  1. 18.13.1 ADC Timing Diagrams
  2. 18.13.2 Post-Processing Block Timings
14. 18.14 Additional Information
15. 18.15 Software
  1. 18.15.1 ADC Examples
16. 18.16 ADC Registers
19Buffered Digital-to-Analog Converter (DAC)
1. 19.1 Introduction
2. 19.2 Using the DAC
3. 19.3 Lock Registers
4. 19.4 Software
  1. 19.4.1 DAC Examples
    1. 19.4.1.1 Buffered DAC Enable - SINGLE_CORE
    2. 19.4.1.2 Buffered DAC Random - SINGLE_CORE
5. 19.5 DAC Registers
20Comparator Subsystem (CMPSS)
1. 20.1 Introduction
2. 20.2 Comparator
3. 20.3 Reference DAC
4. 20.4 Ramp Generator
5. 20.5 Digital Filter
  1. 20.5.1 Filter Initialization Sequence
6. 20.6 Using the CMPSS
7. 20.7 Software
  1. 20.7.1 CMPSS Examples
    1. 20.7.1.1 CMPSS Asynchronous Trip - SINGLE_CORE
    2. 20.7.1.2 CMPSS Digital Filter Configuration - SINGLE_CORE
8. 20.8 CMPSS Registers
21Enhanced Capture (eCAP) and High Resolution Capture (HRCAP)
1. 21.1 Introduction
  1. 21.1.1 Features
  2. 21.1.2 ECAP Related Collateral
2. 21.2 Description
3. 21.3 Configuring Device Pins for the eCAP
4. 21.4 Capture and APWM Operating Mode
5. 21.5 Capture Mode Description
6. 21.6 Application of the eCAP Module
7. 21.7 Application of the APWM Mode
  1. 21.7.1 Example 1 - Simple PWM Generation (Independent Channels)
8. 21.8 High Resolution Capture (HRCAP) Module
9. 21.9 Software
  1. 21.9.1 ECAP Examples
  2. 21.9.2 HRCAP Examples
    1. 21.9.2.1 HRCAP Capture and Calibration Example - SINGLE_CORE
10. 21.10 eCAP Registers
11. 21.11 HRCAP Registers
22Enhanced Pulse Width Modulator (ePWM)
1. 22.1 Introduction
  1. 22.1.1 EPWM Related Collateral
  2. 22.1.2 Submodule Overview
2. 22.2 Configuring Device Pins
3. 22.3 ePWM Modules Overview
4. 22.4 Time-Base (TB) Submodule
  1. 22.4.1 Purpose of the Time-Base Submodule
  2. 22.4.2 Controlling and Monitoring the Time-Base Submodule
  3. 22.4.3 Calculating PWM Period and Frequency
  4. 22.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
  5. 22.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
  6. 22.4.6 Time-Base Counter Modes and Timing Waveforms
  7. 22.4.7 Global Load
5. 22.5 Counter-Compare (CC) Submodule
  1. 22.5.1 Purpose of the Counter-Compare Submodule
  2. 22.5.2 Controlling and Monitoring the Counter-Compare Submodule
  3. 22.5.3 Operational Highlights for the Counter-Compare Submodule
  4. 22.5.4 Count Mode Timing Waveforms
6. 22.6 Action-Qualifier (AQ) Submodule
  1. 22.6.1 Purpose of the Action-Qualifier Submodule
  2. 22.6.2 Action-Qualifier Submodule Control and Status Register Definitions
  3. 22.6.3 Action-Qualifier Event Priority
  4. 22.6.4 AQCTLA and AQCTLB Shadow Mode Operations
  5. 22.6.5 Configuration Requirements for Common Waveforms
7. 22.7 XCMP Complex Waveform Generator Mode
  1. 22.7.1 XCMP Allocation to CMPA and CMPB
  2. 22.7.2 XCMP Shadow Buffers
  3. 22.7.3 XCMP Operation
8. 22.8 Dead-Band Generator (DB) Submodule
  1. 22.8.1 Purpose of the Dead-Band Submodule
  2. 22.8.2 Dead-band Submodule Additional Operating Modes
  3. 22.8.3 Operational Highlights for the Dead-Band Submodule
9. 22.9 PWM Chopper (PC) Submodule
  1. 22.9.1 Purpose of the PWM Chopper Submodule
  2. 22.9.2 Operational Highlights for the PWM Chopper Submodule
  3. 22.9.3 Waveforms
    1. 22.9.3.1 One-Shot Pulse
    2. 22.9.3.2 Duty Cycle Control
10. 22.10 Trip-Zone (TZ) Submodule
  1. 22.10.1 Purpose of the Trip-Zone Submodule
  2. 22.10.2 Operational Highlights for the Trip-Zone Submodule
    1. 22.10.2.1 Trip-Zone Configurations
  3. 22.10.3 Generating Trip Event Interrupts
11. 22.11 Diode Emulation (DE) Submodule
  1. 22.11.1 DEACTIVE Mode
  2. 22.11.2 Exiting DE Mode
  3. 22.11.3 Re-Entering DE Mode
  4. 22.11.4 DE Monitor
12. 22.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
  1. 22.12.1 Minimum Dead-Band (MINDB)
  2. 22.12.2 Illegal Combo Logic (ICL)
13. 22.13 Event-Trigger (ET) Submodule
  1. 22.13.1 Operational Overview of the ePWM Event-Trigger Submodule
14. 22.14 Digital Compare (DC) Submodule
  1. 22.14.1 Purpose of the Digital Compare Submodule
  2. 22.14.2 Enhanced Trip Action Using CMPSS
  3. 22.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
  4. 22.14.4 Operation Highlights of the Digital Compare Submodule
15. 22.15 ePWM Crossbar (X-BAR)
16. 22.16 Applications to Power Topologies
  1. 22.16.1 Overview of Multiple Modules
  2. 22.16.2 Key Configuration Capabilities
  3. 22.16.3 Controlling Multiple Buck Converters With Independent Frequencies
  4. 22.16.4 Controlling Multiple Buck Converters With Same Frequencies
  5. 22.16.5 Controlling Multiple Half H-Bridge (HHB) Converters
  6. 22.16.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
  7. 22.16.7 Practical Applications Using Phase Control Between PWM Modules
  8. 22.16.8 Controlling a 3-Phase Interleaved DC/DC Converter
  9. 22.16.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
  10. 22.16.10 Controlling a Peak Current Mode Controlled Buck Module
  11. 22.16.11 Controlling H-Bridge LLC Resonant Converter
17. 22.17 Register Lock Protection
18. 22.18 High-Resolution Pulse Width Modulator (HRPWM)
  1. 22.18.1 Operational Description of HRPWM
  2. 22.18.2 SFO Library Software - SFO_TI_Build_V8.lib
    1. 22.18.2.1 Scale Factor Optimizer Function - int SFO()
    2. 22.18.2.2 Software Usage
      1. 22.18.2.2.1 A Sample of How to Add "Include" Files
      2. 1198
      3. 22.18.2.2.2 Declaring an Element
      4. 1200
      5. 22.18.2.2.3 Initializing With a Scale Factor Value
      6. 1202
      7. 22.18.2.2.4 SFO Function Calls
19. 22.19 Software
  1. 22.19.1 EPWM Examples
  2. 22.19.2 HRPWM Examples
20. 22.20 ePWM Registers
  1. 22.20.1 EPWM Base Address Table
  2. 22.20.2 EPWM_REGS Registers
  3. 22.20.3 EPWM_XCMP_REGS Registers
  4. 22.20.4 DE_REGS Registers
  5. 22.20.5 MINDB_LUT_REGS Registers
  6. 22.20.6 HRPWMCAL_REGS Registers
  7. 22.20.7 Register to Driverlib Function Mapping
23Enhanced Quadrature Encoder Pulse (eQEP)
1. 23.1 Introduction
  1. 23.1.1 EQEP Related Collateral
2. 23.2 Configuring Device Pins
3. 23.3 Description
4. 23.4 Quadrature Decoder Unit (QDU)
5. 23.5 Position Counter and Control Unit (PCCU)
6. 23.6 eQEP Edge Capture Unit
7. 23.7 eQEP Watchdog
8. 23.8 eQEP Unit Timer Base
9. 23.9 QMA Module
  1. 23.9.1 Modes of Operation
    1. 23.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
    2. 23.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
  2. 23.9.2 Interrupt and Error Generation
10. 23.10 eQEP Interrupt Structure
11. 23.11 Software
  1. 23.11.1 EQEP Examples
    1. 23.11.1.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
    2. 23.11.1.2 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
12. 23.12 eQEP Registers
24Sigma Delta Filter Module (SDFM)
1. 24.1 Introduction
2. 24.2 Configuring Device Pins
3. 24.3 Input Qualification
4. 24.4 Input Control Unit
5. 24.5 SDFM Clock Control
6. 24.6 Sinc Filter
  1. 24.6.1 Data Rate and Latency of the Sinc Filter
7. 24.7 Data (Primary) Filter Unit
8. 24.8 Comparator (Secondary) Filter Unit
9. 24.9 Theoretical SDFM Filter Output
10. 24.10 Interrupt Unit
  1. 24.10.1 SDFM (SDyERR) Interrupt Sources
  2. 24.10.2 Data Ready (DRINT) Interrupt Sources
11. 24.11 Software
  1. 24.11.1 SDFM Examples
12. 24.12 SDFM Registers
25Controller Area Network (CAN)
1. 25.1 Introduction
2. 25.2 Functional Description
  1. 25.2.1 Configuring Device Pins
  2. 25.2.2 Address/Data Bus Bridge
3. 25.3 Operating Modes
4. 25.4 Multiple Clock Source
5. 25.5 Interrupt Functionality
6. 25.6 DMA Functionality
7. 25.7 Parity Check Mechanism
  1. 25.7.1 Behavior on Parity Error
8. 25.8 Debug Mode
9. 25.9 Module Initialization
10. 25.10 Configuration of Message Objects
11. 25.11 Message Handling
12. 25.12 CAN Bit Timing
  1. 25.12.1 Bit Time and Bit Rate
  2. 25.12.2 Configuration of the CAN Bit Timing
13. 25.13 Message Interface Register Sets
  1. 25.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
  2. 25.13.2 Message Interface Register Set 3 (IF3)
14. 25.14 Message RAM
15. 25.15 Software
  1. 25.15.1 CAN Examples
16. 25.16 CAN Registers
26EtherCAT® SubordinateDevice Controller (ESC)
1. 26.1 Introduction
2. 26.2 ESC and ESCSS Description
3. 26.3 Software Initialization Sequence and Allocating Ownership
4. 26.4 ESC Configuration Constants
5. 26.5 EtherCAT IP Registers
27Fast Serial Interface (FSI)
1. 27.1 Introduction
  1. 27.1.1 FSI Related Collateral
  2. 27.1.2 FSI Features
2. 27.2 System-level Integration
3. 27.3 FSI Functional Description
4. 27.4 FSI Programing Guide
5. 27.5 Software
  1. 27.5.1 FSI Examples
    1. 27.5.1.1 FSI Loopback:CPU Control - SINGLE_CORE
    2. 27.5.1.2 FSI data transfers upon CPU Timer event - SINGLE_CORE
6. 27.6 FSI Registers
28Inter-Integrated Circuit Module (I2C)
1. 28.1 Introduction
2. 28.2 Configuring Device Pins
3. 28.3 I2C Module Operational Details
4. 28.4 Interrupt Requests Generated by the I2C Module
  1. 28.4.1 Basic I2C Interrupt Requests
  2. 28.4.2 I2C FIFO Interrupts
5. 28.5 Resetting or Disabling the I2C Module
6. 28.6 Software
  1. 28.6.1 I2C Examples
7. 28.7 I2C Registers
29Power Management Bus Module (PMBus)
1. 29.1 Introduction
2. 29.2 Configuring Device Pins
3. 29.3 Target Mode Operation
  1. 29.3.1 Configuration
  2. 29.3.2 Message Handling
4. 29.4 Controller Mode Operation
  1. 29.4.1 Configuration
  2. 29.4.2 Message Handling
5. 29.5 PMBUS Registers
30Serial Communications Interface (SCI)
1. 30.1 Introduction
2. 30.2 Architecture
3. 30.3 SCI Module Signal Summary
4. 30.4 Configuring Device Pins
5. 30.5 Multiprocessor and Asynchronous Communication Modes
6. 30.6 SCI Programmable Data Format
7. 30.7 SCI Multiprocessor Communication
8. 30.8 Idle-Line Multiprocessor Mode
9. 30.9 Address-Bit Multiprocessor Mode
  1. 30.9.1 Sending an Address
10. 30.10 SCI Communication Format
  1. 30.10.1 Receiver Signals in Communication Modes
  2. 30.10.2 Transmitter Signals in Communication Modes
11. 30.11 SCI Port Interrupts
  1. 30.11.1 Break Detect
12. 30.12 SCI Baud Rate Calculations
13. 30.13 SCI Enhanced Features
14. 30.14 Software
  1. 30.14.1 SCI Examples
15. 30.15 SCI Registers
31Serial Peripheral Interface (SPI)
1. 31.1 Introduction
2. 31.2 System-Level Integration
3. 31.3 SPI Operation
4. 31.4 Programming Procedure
5. 31.5 Software
  1. 31.5.1 SPI Examples
6. 31.6 SPI Registers
32Universal Serial Bus (USB) Controller
1. 32.1 Introduction
2. 32.2 Functional Description
3. 32.3 Initialization and Configuration
  1. 32.3.1 Pin Configuration
  2. 32.3.2 Endpoint Configuration
4. 32.4 USB Global Interrupts
5. 32.5 Software
  1. 32.5.1 USB Examples
6. 32.6 USB Registers
33Advanced Encryption Standard (AES) Accelerator
1. 33.1 Introduction
  1. 33.1.1 AES Block Diagram
  2. 33.1.2 AES Algorithm
2. 33.2 AES Operating Modes
3. 33.3 Extended and Combined Modes of Operations
4. 33.4 AES Module Programming Guide
  1. 33.4.1 AES Low-Level Programming Models
5. 33.5 Software
  1. 33.5.1 AES Examples
6. 33.6 AES Registers
34Embedded Pattern Generator (EPG)
1. 34.1 Introduction
2. 34.2 Clock Generator Modules
  1. 34.2.1 DCLK (50% duty cycle clock)
  2. 34.2.2 Clock Stop
3. 34.3 Signal Generator Module
4. 34.4 EPG Peripheral Signal Mux Selection
5. 34.5 Application Software Notes
6. 34.6 EPG Example Use Cases
7. 34.7 EPG Interrupt
8. 34.8 Software
  1. 34.8.1 EPG Examples
9. 34.9 EPG Registers
35Modular Controller Area Network (MCAN)
1. 35.1 MCAN Introduction
  1. 35.1.1 MCAN Related Collateral
  2. 35.1.2 MCAN Features
2. 35.2 MCAN Environment
3. 35.3 CAN Network Basics
4. 35.4 MCAN Integration
5. 35.5 MCAN Functional Description
6. 35.6 Software
  1. 35.6.1 MCAN Examples
    1. 35.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
    2. 35.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
7. 35.7 MCAN Registers
36Universal Asynchronous Receiver/Transmitter (UART)
1. 36.1 Introduction
  1. 36.1.1 Features
  2. 36.1.2 Block Diagram
2. 36.2 Functional Description
3. 36.3 Initialization and Configuration
4. 36.4 Software
  1. 36.4.1 UART Examples
5. 36.5 UART Registers
37Local Interconnect Network (LIN)
1. 37.1 LIN Overview
2. 37.2 Serial Communications Interface Module
3. 37.3 Local Interconnect Network Module
4. 37.4 Low-Power Mode
5. 37.5 Emulation Mode
6. 37.6 Software
  1. 37.6.1 LIN Examples
7. 37.7 SCI/LIN Registers
38Lockstep Compare Module (LCM)
1. 38.1 Introduction
  1. 38.1.1 Features
  2. 38.1.2 Block Diagram
2. 38.2 Enabling LCM Comparators
3. 38.3 Disabling LCM Redundant Module
4. 38.4 LCM Error Handling
5. 38.5 LCM Error Flags
6. 38.6 Debug Mode with LCM
7. 38.7 Register Parity Error Protection
8. 38.8 Functional Logic
9. 38.9 LCM Registers
39Revision History

6.3.7 BGCRC Golden CRC-32 Value Computation

The C28x is a little-endian, 16-bit word addressable CPU. Therefore, the 32-bit value of 0x12345678 stored at address 0x100 is stored in the C28x memory as shown in Table 6-2.

Table 6-2 Data Address Location Example 1

Address	0x100	0x101
Data	0x5678	0x1234

The BGCRC order of byte calculations of the above example is 0x78, 0x56, 0x34, 0x12 and yields 0x6A330D2D. The 32-bit polynomial 0x04C11DB7 is used with an initialization vector of 0x00000000. The following code snippet shows the effective bit processing. Processing for all 32-bits within a word occurs in a single cycle within the BGCRC hardware.

seed = 0x0UL; //Initialize With Seed
poly = 0x04C11DB7UL: //32-Bit Polynomial
crc32 = seed;

for(i=0; i<dataSize; i++)
{
         byteSwappedData = ((data[i] & 0x000000FF) << 24)|
                         = ((data[i] & 0x0000FF00) << 8) |
                         = ((data[i] & 0x00FF0000) >> 8) |
                         = ((data[i] & 0xFF000000) >> 24);
		
		crc32 = byteSwappedData^crc32;
		for(j=0; j<32; j++)
		{
			if(crc32 & 0x80000000) crc32 = (crc32 << 1)^poly;
			else crc32 = crc32 << 1;
			
			crc32 = crc32 & 0xFFFFFFFF;
		}
}

A second example (Table 6-3) with two 32-bit words, 0x12345678 and 0x9ABCDEF0 at address 0x100 and 0x102 successively, calculates the bytes in the order 0x78, 0x56, 0x34, 0x12, 0xDE, 0xBC, and 0x9A and yield 0x7E0B4164.

Table 6-3 Data Address Location Example 2

Address	0x100	0x101	0x102	0x103
Data	0x5678	0x1234	0xDEF0	0x9ABC

All data input to the BGCRC must align to a 32-bit boundary, both in the starting address and the size. It is possible to include 16-bit data within the span of data; however, when the data is read by the BGCRC, it always assume 32-bits and conform to the above calculation order. For example, if two 16-bit words (0xA0B1 and 0xC2D3) were placed in between the previous two 32-bit words (Table 6-4), the calculations are performed in byte order 0x78, 0x56, 0x34, 0x12, 0xB1, 0xA0, 0xD3, 0xC2, 0xF0, 0xDE, 0xBC, and 0x9A and yield 0x2AEFD987.

Table 6-4 Data Address Location Example 3

Address	0x100	0x101	0x102	0x103	0x104	0x105
Data	0x5678	0x1234	0xA0B1	0xC2D3	0xDEF0	0x9ABC