SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
The operation of the EMIF's asynchronous interface can be configured by programming the appropriate register fields. The reset value and bit position for each register field can be found in Section 11.5. The following tables list the register fields that can be programmed and describe the purpose of each field. These registers can be programmed prior to accessing the external memory, and the transfer following a write to these registers uses the new configuration.
| Parameter | Description |
|---|---|
| SS | Select Strobe mode. This bit selects the EMIF's mode of operation in the following way:
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| EW | Extended Wait Mode enable.
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| W_SETUP/R_SETUP | Read/Write setup widths. These fields define the number of EMIF clock cycles of setup time for the address pins (EM1A), byte enables (EM1DQM), and asynchronous chip enable (EM1CS[4:2]) before the read strobe pin (EM103) or write strobe pin (EM1WE) falls, minus one cycle. For writes, the W_SETUP field also defines the setup time for the data pins (EM1D). Refer to the asynchronous device 's data sheet to determine the appropriate setting for this field. |
| W_STROBE/R_STROBE | Read/Write strobe widths. These fields define the number of EMIF clock cycles between the falling and rising of the read strobe pin (EM103) or write strobe pin (EM1WEn), minus one cycle. If Extended Wait Mode is enabled by setting the EW field in the asynchronous n configuration register (ASYNC_CSn_CR), these fields must be set to a value greater than zero. Refer to the data manual of the external asynchronous device to determine the appropriate setting for this field. |
| W_HOLD/R_HOLD | Read/Write hold widths. These fields define the number of EMIF clock cycles of hold time for the address pins (EM1A and EM1BA), byte enables (EM1DQM), and asynchronous chip enable (EM1CS[4:2]) after the read strobe pin (EM103) or write strobe pin (EM1WE) rises, minus one cycle. For writes, the W_HOLD field also defines the hold time for the data pins (EM1D). Refer to the data manual of the external asynchronous device to determine the appropriate setting for this field. |
| TA | Minimum turnaround time. This field defines the minimum number of EMIF clock cycles between asynchronous reads and writes, minus one cycle. The purpose of this feature is to avoid contention on the bus. The value written to this field also determines the number of cycles that are inserted between asynchronous accesses and SDRAM accesses. Refer to the data manual of the external asynchronous device to determine the appropriate setting for this field. |
| ASIZE | Asynchronous Device Bus Width.
This field determines the data bus width of the asynchronous interface in the following way:
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| Parameter | Description |
|---|---|
| WPn | EM_WAIT Polarity.
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| MAX_EXT_WAIT | Maximum Extended Wait Cycles.
This field configures the number of EMIF clock cycles the EMIF waits for the EM1WAIT pin to be deactivated during the strobe period of an access cycle. The maximum number of EMIF clock cycles the EMIF waits is determined by the following formula: Maximum Extended Wait Cycles = (MAX_EXT_WAIT + 1) × 16 If the EM1WAIT pin is not deactivated within the time specified by this field, the EMIF resumes the access cycle, registering whatever data is on the bus and proceeding to the hold period of the access cycle. This situation is referred to as an Asynchronous Timeout. An Asynchronous Timeout generates an interrupt, if the interrupt has been enabled in the EMIF interrupt mask set register (INT_MSK_SET). Refer to Section 11.2.9.1 for more information about EMIF interrupts. |
| Parameter | Description |
|---|---|
| WR_MASK_SET | Wait Rise Mask Set. Writing a 1 enables an interrupt to be generated when a rising edge on EM1WAIT occurs. |
| AT_MASK_SET | Asynchronous Timeout Mask Set. Writing a 1 to this bit enables an interrupt to be generated when an Asynchronous Timeout occurs. |
| Parameter | Description |
|---|---|
| WR_MASK_CLR | Wait Rise Mask Clear. Writing a 1 to this bit disables the interrupt, clearing the WR_MASK_SET bit in EMIF interrupt mask set register (INT_MSK_SET). |
| AT_MASK_CLR | Asynchronous Timeout Mask Clear. Writing a 1 to this bit prevents an interrupt from being generated when an Asynchronous Timeout occurs. |