SPRUIZ1B July 2023 – August 2024 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
The block diagram in Figure 22-5 shows the critical signals and registers of the time-base submodule. Table 22-2 provides descriptions of the key signals associated with the time-base submodule.
Signal | Description |
---|---|
EPWMxSYNCI | Time-base synchronization input. |
Input pulse used to synchronize the time-base counter with the counter of other ePWM modules. For more information on all of the signals available for synchronization, see EPWMSYNCINSEL. For information on the synchronization order of a particular device, see Section 22.4.3.3. | |
EPWMxSYNCO | Time-base synchronization output. |
This output pulse is used to synchronize the counter of other ePWM modules. Using EPWMSYNCOUTEN, TBCTL2, TBCTL3 and GLDCTL2, the source of the output pulse is selected. | |
EPWMxSYNCPER | Time-base peripheral synchronization output. |
This output signal is used to synchronize the GPDAC and CMPSS to the EPWM. The output signal can be configured using the HRPCTL register. Note that this signal has no relation with the HRPWM. | |
CTR = PRD | Time-base counter equal to the specified period. |
This signal is generated whenever the counter value is equal to the active period register value. That is when TBCTR = TBPRD. | |
CTR = Zero | Time-base counter equal to zero |
This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x00. | |
CTR = CMPB | Time-base counter equal to active counter-compare B register (TBCTR = CMPB). |
This event is generated by the counter-compare submodule and used by the synchronization out logic | |
CTR_dir | Time-base counter direction. |
Indicates the current direction of the ePWM's time-base counter. The signal is high when the counter is increasing and the signal is low when the counter is decreasing. | |
CTR_max | Time-base counter equal max value. (TBCTR = 0xFFFF) |
Generated event when the TBCTR value reaches the maximum value. This signal is only used only as a status bit | |
TBCLK | Time-base clock. |
This is a prescaled version of the ePWM clock (EPWMCLK) and is used by all submodules within the ePWM. This clock determines the rate at which time-base counter increments or decrements. |