Refer to your device
SysCtl_setAuxClock() function inside C2000Ware installation for an example.
If USB functionality is needed, the
auxiliary clock (AUXPLLCLK) must be configured to produce 60MHz. The procedure is
similar to the system clock setup:
- Bypass the PLL by clearing
AUXPLLCTL1[PLLCLKEN] and wait for at least 120 CPU clock cycles by adding
120 NOP instructions..
- Power down the PLL by writing to
AUXPLLCTL1.PLLEN = 0 and wait for at least 60 CPU clock cycles by adding 60 NOP
instructions.
- Select the reference clock source
(AUXOSCCLK) by writing to CLKSRCCTL2.AUXOSCCLKSRCSEL and wait for at least
60 CPU clock cycles by adding 60 NOP instructions.
- Set the IMULT, REFDIV, and ODIV
simultaneously by writing 32-bit value in AUXPLLMULT at once. This automatically
enables the PLL. Be sure the settings for multiplier and dividers do not violate
the frequency specifications as defined in the TMS320F28P65x
Real-Time Microcontrollers Data Sheet.
- Wait for PLL to lock by polling
for lock status bit to go high (AUXPLLSTS.LOCKS = 1)
- Configure DCC with reference
clock as AUXOSCCLK and clock under measurement as AUXPLLRAWCLK, and verify the
frequency of the PLL. If the frequency is out of range, stop here and
troubleshoot. Refer to Chapter 9 for more information on the configuration and usage.
- Connect the auxiliary PLL output
clock (AUXPLLRAWCLK) to AUXPLLCLK by writing a 1 to AUXPLLCTL1.PLLCLKEN.
The auxiliary clock configuration can
be changed at run time. Changing the AUXOSCCLK source automatically bypasses the PLL
and sets the multiplier to zero. Changing the multiplier from one non-zero value to
another temporarily bypasses the PLL until the PLL re-locks.
Note:
- AUXPLL must be bypassed and
powered down manually before changing the AUXOSCCLK source.
- At least 120 CPU clock cycles
delay is needed after bypassing PLL, that is, AUXPLLCTL1.PLLCLKEN = 0.
- At least 60 CPU clock cycles
delay is needed after PLL is powered down, that is,
AUXPLLCTL1.PLLEN = 0.
- At least 60 CPU clock cycles
delay is needed after AUXOSSCLK source is changed.
- AUXPLL SLIP bit is not
supported. DCC can be used to check the validity of the AUXPLL clock. This
feature is included as part of SysCtl_setAuxClock() function inside
C2000Ware.