SPRUJ10D May   2022  – September 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 2.1 Sitara MCU+ Academy
    2. 2.2 If You Need Assistance
    3. 2.3 Important Usage Notes
  5. 2Kit Overview
    1. 3.1 Kit Contents
    2. 3.2 Key Features
    3. 3.3 Component Identification
    4. 3.4 BoosterPacks
    5. 3.5 Compliance
    6. 3.6 Security
  6. 3Board Setup
    1. 4.1 Power Requirements
      1. 4.1.1 Power Input Using USB Type-C Connector
      2. 4.1.2 Power Status LEDs
      3. 4.1.3 Power Tree
    2. 4.2 Push Buttons
    3. 4.3 Boot Mode Selection
  7. 4Hardware Description
    1. 5.1  Functional Block Diagram
    2. 5.2  GPIO Mapping
    3. 5.3  Reset
    4. 5.4  Clock
    5. 5.5  Memory Interface
      1. 5.5.1 QSPI
      2. 5.5.2 Board ID EEPROM
    6. 5.6  Ethernet Interface
      1. 5.6.1 Ethernet PHY #1 - CPSW RGMII/ICSSM
      2. 5.6.2 Ethernet PHY #2 - CPSW RGMII/ICSSM
      3. 5.6.3 LED Indication in RJ45 Connector
    7. 5.7  I2C
    8. 5.8  Industrial Application LEDs
    9. 5.9  SPI
    10. 5.10 UART
    11. 5.11 MCAN
    12. 5.12 FSI
    13. 5.13 JTAG
    14. 5.14 Test Automation Header
    15. 5.15 LIN
    16. 5.16 MMC
    17. 5.17 ADC and DAC
    18. 5.18 EQEP and SDFM
    19. 5.19 EPWM
    20. 5.20 BoosterPack Headers
    21. 5.21 Pinmux Mapping
  8. 5References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  9. 6Revision History

4.3 Reset

Figure 4-2 shows the reset architecture of the AM263x LaunchPad

GUID-20220501-SS0I-Z7FW-4Z1Z-RVSC0K8XKDQF-low.png Figure 4-2 Reset Architecture

The AM263x LaunchPad has the following resets:

  • PORz is the Power On Reset
  • WARMRESETn is the warm reset

GUID-20220501-SS0I-ZQMQ-7KDT-2X51LHFQXBPL-low.png Figure 4-3 PORz Reset Signal Tree

The PORz signal is driven by a 3-input AND gate that generates a power on reset for the MAIN domain when:

  • The 3.3V buck converter (TPS62913) power good output is driven low by having an output voltage that is below the power-good threshold.
  • The 1.2V buck converter (TPS62912) power good output is driven low by having an output voltage that is below the power-good threshold.
  • The user push button (SW2) is pressed.
  • A P-Channel MOSFET gate's signal is logic LOW which causes V_GS of the PMOS to be less than zero and so the PORz signal connects to the PMOS drain which is tied directly to ground. The signals that can create the logic LOW input to the PMOS gate are:
    • TA_PORZ output from the Test Automation header
    • BP_PORZ output from either of the BoosterPack sites.

The PORz signal is tied to:

  • AM263x SoC PORz input
  • BOOTMODE State Driver's output enable input
    • There is an RC filter to create a 1ms delay from GND to 3.0V such that the SOP State Driver's output enable input is low longer than the required SOP hold time following a PORz de-assertion.

There is a Test-Automation PORz Override header that enables the ability to hold TA_GPIO3 low when a jumper is installed. This enables the BOOTMODE Control from the Test Automation Header.

GUID-20220501-SS0I-WF6W-SG0S-MC0J0FBMKF8Q-low.png Figure 4-4 WARMRESETn Reset Signal Tree

The WARMRESETn signal creates a warm reset to the MAIN domain when:

  • The user push button (SW3) is presed.
  • The Test Automation Header outputs a logic LOW signal (TA_RESETz) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the RESETz signal connects to the PMOS drain which is tied directly to ground.

The WARMRESETn signal is tied to:

  • AM263x SoC WARMRESETN output
  • RESETN_PB signal that is created from push button + PMOS logic
  • Micro SD Load Switch control input via a 2 input AND Gate with an AM263x SoC driven GPIO signal (GPIO122)
  • Both Ethernet PHY's reset input

The AM263x LaunchPad also has an external interrupt to the SoC , INT1, that occurs when:

  • The user push button (SW4) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_GPIO1) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the INTn signal connects to the PMOS drain which is tied directly to ground.