SPRUJ12F August   2021  – January 2024 AM2431 , AM2432 , AM2434

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 1.1 If You Need Assistance
    2. 1.2 Important Usage Notes
  5. 2Kit Overview
    1. 2.1 Kit Contents
    2. 2.2 Key Features
    3. 2.3 Component Identification
    4. 2.4 BoosterPacks
    5. 2.5 Compliance
    6. 2.6 Security
  6. 3Board Setup
    1. 3.1 Power Requirements
      1. 3.1.1 Power Input Using USB Type-C Connector
      2. 3.1.2 Power Status LED's
      3. 3.1.3 Power Tree
      4. 3.1.4 Power Sequence
    2. 3.2 Push Buttons
    3. 3.3 Boot Mode Selection
  7. 4Hardware Description
    1. 4.1  Functional Block Diagram
    2. 4.2  BoosterPack Headers
      1. 4.2.1 Pinmux for BoosterPack
    3. 4.3  GPIO Mapping
    4. 4.4  Reset
    5. 4.5  Clock
    6. 4.6  Memory Interface
      1. 4.6.1 QSPI Interface
      2. 4.6.2 Board ID EEPROM
    7. 4.7  Ethernet Interface
      1. 4.7.1 Ethernet PHY Strapping
      2. 4.7.2 Ethernet PHY - Power, Clock, Reset, Interrupt
      3. 4.7.3 LED indication in Ethernet RJ45 Connector
    8. 4.8  USB 2.0 Interface
    9. 4.9  I2C Interface
    10. 4.10 Industrial Application LEDs
    11. 4.11 UART Interface
    12. 4.12 eQEP Interface
    13. 4.13 CAN Interface
    14. 4.14 FSI Interface
    15. 4.15 JTAG Emulation
    16. 4.16 Test Automation Interface
    17. 4.17 SPI Interface
  8. 5References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used in This Design
  9.   A E3 Design Changes
  10.   B Revision A Design Changes
  11.   Revision History

A E3 Design Changes

The AM243x LaunchPad had various design changes for the E3 revision of the board. The changes are listed in Table 7-5.

  1. RJ45 Connector Component Replaced
    Table A-1 E3 RJ45 Connector
    AM243x LP E2 AM243x LP E3
    74991116144A from Wurth Electronics LPJG16314A4NL from Link-PP with common center tap
  2. eFUSE Programming Voltage LDO Driven by a Header Rather than GPIO
    1. The E2 revision of the AM243x Launchpad used GPIO0_53 to enable the VPP regulator for eFUSE Programming. In the E3 revision, the enable line is connected to pin 2 of a two pin header (J22.2). Connecting a jumper across the two pins enables the LDO.
    2. A resistor was added in the E3 revision to pull-up pin one (J22.1) of the VPP enable header to VSYS_3V3.
  3. GPIO Mapping Changes
    1. The E3 revision made various changes to the GPIO mapping. Table 6-2 describes the changes.
      Table A-2 E3 GPIO Mapping
      Package Signal Name GPIO Number E2 Net Name E3 Net Name Description
      GPMC_AD13 GPIO0_28 FSI/BP_MUX_SEL GPIO_RGMII1_PHY_RSTn To reset the RGMII1 Ethernet PHY
      GPMC_AD12 GPIO0_27 USER_LED2 PRG_CPSW_RGMII1_MUX_SEL To select the RGMII1 path between PRG and CPSW
      GPMC0_AD11 GPIO0_26 USER_LED1 FSI/BP_MUX_SEL To select the functionality of GPMC0_AD8 and GPMC0_AD9 pins as FSI_RX or PWM
      PRG1_PRU1_GPO5 GPIO0_70 PRG_CPSW_RGMII1_MUX_SEL PRG1_CPSW_ETH2_LED_1000/RX_ER Ethernet PHY2 RX ER indication to SoC
      PRG1_PRU1_GPO8 GPIO0_73 GPIO_RGMII1_PHY_RSTn PRG1_CPSW_ETH2_LED_LINK Ethernet PHY2 RX link indication to SoC
      PRG1_PRU0_GPO5 GPIO0_50 GPIO0_50 PRG1_CPSW_ETH1_LED_1000/RX_ER Ethernet PHY1 RX ER indication to SoC
      PRG1_PRU0_GPO8 GPIO0_53 VPP_1V8_REG_EN PRG1_CPSW_ETH1_LED_LINK Ethernet PHY1 RX link indication to SoC
      PRG1_PRU0_GPO9 GPIO0_54 CPSW_RGMII1_TX_CTL PRG1_CPSW_ETH1_LED_ACT Ethernet PHY1 MII COL indication to SoC
      PRG1_PRU1_GPO9 GPIO0_74 CPSW_RGMII1_TD1 PRG1_CPSW_ETH2_LED_ACT Ethernet PHY2 MII COL indication to SoC
      Note: GPIO Mapping for signals not present in this table have the same mapping for E2 and E3 revisions of the LaunchPad
  4. Bootmode Isolation Buffer Component Change
    1. The E2 Revision of the AM243x LaunchPad only supported input signals for balls connected to the Bootmode isolation buffer (U32) since the DIR pin was connected to ground. In E3 the Bootmode isolation buffer is changed from SN74AVC8T245PWR to TXB0106PWR. Because the E3 isolation buffer is bi-directional, input and output signals are supported.
    2. The TXB0106PWR OE enable pin places all outputs in a high impedence state when OE = low. The inverter gate was removed in the E3 Revision because the OE pin can be connected directly to PORz.
    3. The BOOTMODE0/2/10 signals connected to the buffer had the respective pull-up or pull-down resistor updated from 10kΩ to 49.9kΩ.
  5. Ethernet PHY Connections
    1. The following Ethernet PHY signals were not connected to the AM243x GPIO in the E2 Revision:
      • PRG1_CPSW_ETH1_LED_LINK
      • PRG1_CPSW_ETH2_LED_LINK
      • PRG1_CPSW_ETH1_LED_1000/RX_ER
      • PRG1_CPSW_ETH2_LED_1000/RX_ER
      • PRG1_CPSW_ETH1_LED_ACT
      • PRG1_CPSW_ETH2_LED_ACT
    2. Each unconnected signal was routed to a SoC GPIO signal with the mapping discussed in Table 6-3.
      Table A-3 E3 Ethernet PHY Signal Mapping
      Package Signal Name GPIO Number E3 Net Name Description
      PRG1_PRU1_GPO5 GPIO0_70 PRG1_CPSW_ETH2_LED_1000/RX_ER Ethernet PHY2 RX ER indication to SoC
      PRG1_PRU1_GPO8 GPIO0_73 PRG1_CPSW_ETH2_LED_LINK Ethernet PHY2 RX link indication to SoC
      PRG1_PRU0_GPO5 GPIO0_50 PRG1_CPSW_ETH1_LED_1000/RX_ER Ethernet PHY1 RX ER indication to SoC
      PRG1_PRU0_GPO8 GPIO0_53 PRG1_CPSW_ETH1_LED_LINK Ethernet PHY1 RX link indication to SoC
      PRG1_PRU0_GPO9 GPIO0_54 PRG1_CPSW_ETH1_LED_ACT Ethernet PHY1 MII COL indication to SoC
      PRG1_PRU1_GPO9 GPIO0_74 PRG1_CPSW_ETH2_LED_ACT Ethernet PHY2 MII COL indication to SoC
    3. The ETH<n>_LED_ACT signals are connected via a resistor mux with the logic: discussed in Table 6-4.
      Table A-4 E3 LED ACT Signal Resistor Mounting
      Interface Mount DNI
      CPSW_RGMII1_TX_CTL & CPWS_RGMII1_TD1 (Default) R595, R597 R594, R596
      PRG1_CPSW_ETH1_LED_ACT & PRG1_CPSW_ETH2_LED_ACT R594, R596 R595, R597