SPRUJ12F August   2021  – January 2024 AM2431 , AM2432 , AM2434

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 1.1 If You Need Assistance
    2. 1.2 Important Usage Notes
  5. 2Kit Overview
    1. 2.1 Kit Contents
    2. 2.2 Key Features
    3. 2.3 Component Identification
    4. 2.4 BoosterPacks
    5. 2.5 Compliance
    6. 2.6 Security
  6. 3Board Setup
    1. 3.1 Power Requirements
      1. 3.1.1 Power Input Using USB Type-C Connector
      2. 3.1.2 Power Status LED's
      3. 3.1.3 Power Tree
      4. 3.1.4 Power Sequence
    2. 3.2 Push Buttons
    3. 3.3 Boot Mode Selection
  7. 4Hardware Description
    1. 4.1  Functional Block Diagram
    2. 4.2  BoosterPack Headers
      1. 4.2.1 Pinmux for BoosterPack
    3. 4.3  GPIO Mapping
    4. 4.4  Reset
    5. 4.5  Clock
    6. 4.6  Memory Interface
      1. 4.6.1 QSPI Interface
      2. 4.6.2 Board ID EEPROM
    7. 4.7  Ethernet Interface
      1. 4.7.1 Ethernet PHY Strapping
      2. 4.7.2 Ethernet PHY - Power, Clock, Reset, Interrupt
      3. 4.7.3 LED indication in Ethernet RJ45 Connector
    8. 4.8  USB 2.0 Interface
    9. 4.9  I2C Interface
    10. 4.10 Industrial Application LEDs
    11. 4.11 UART Interface
    12. 4.12 eQEP Interface
    13. 4.13 CAN Interface
    14. 4.14 FSI Interface
    15. 4.15 JTAG Emulation
    16. 4.16 Test Automation Interface
    17. 4.17 SPI Interface
  8. 5References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used in This Design
  9.   A E3 Design Changes
  10.   B Revision A Design Changes
  11.   Revision History

4.14 FSI Interface

The LaunchPad supports one FSI Interface from the SoC that terminates to a 2x5 header (J16). The 2x5 header has a 3.3 V supply. A 1:2 active mux IC (TMUX154EDGSR) is used to interface the signals between the FSI header and the BoosterPack header as both the FSI and EHRPWM signals are internally muxed inside the SoC.

GUID-20210719-CA0I-FBKX-CLD4-FLWTLJNDCCCZ-low.png Figure 4-23 FSI Interface
Table 4-19 FSI Header Pin Description
Pin Number Signal
J16.1 FSI_RX0_CLK
J16.2 FSI_TX0_CLK
J16.3 GND
J16.4 GND
J16.5 FSI_RX0_D0
J16.6 FSI_TX0_D0
J16.7 FSI_RX0_D1
J16.8 FSI_TX0_D1
J16.9 No connection
J16.10 VSYS_3V3
GUID-20210719-CA0I-J1ZV-4P8S-WTFTJDV8F2KZ-low.png Figure 4-24 FSI Header
GUID-20210719-CA0I-2J2L-Z8KQ-K6BBB0B5WS4F-low.png Figure 4-25 FSI or BoosterPack Mux Selection Circuit