SPRUJ12F August   2021  – January 2024 AM2431 , AM2432 , AM2434

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 1.1 If You Need Assistance
    2. 1.2 Important Usage Notes
  5. 2Kit Overview
    1. 2.1 Kit Contents
    2. 2.2 Key Features
    3. 2.3 Component Identification
    4. 2.4 BoosterPacks
    5. 2.5 Compliance
    6. 2.6 Security
  6. 3Board Setup
    1. 3.1 Power Requirements
      1. 3.1.1 Power Input Using USB Type-C Connector
      2. 3.1.2 Power Status LED's
      3. 3.1.3 Power Tree
      4. 3.1.4 Power Sequence
    2. 3.2 Push Buttons
    3. 3.3 Boot Mode Selection
  7. 4Hardware Description
    1. 4.1  Functional Block Diagram
    2. 4.2  BoosterPack Headers
      1. 4.2.1 Pinmux for BoosterPack
    3. 4.3  GPIO Mapping
    4. 4.4  Reset
    5. 4.5  Clock
    6. 4.6  Memory Interface
      1. 4.6.1 QSPI Interface
      2. 4.6.2 Board ID EEPROM
    7. 4.7  Ethernet Interface
      1. 4.7.1 Ethernet PHY Strapping
      2. 4.7.2 Ethernet PHY - Power, Clock, Reset, Interrupt
      3. 4.7.3 LED indication in Ethernet RJ45 Connector
    8. 4.8  USB 2.0 Interface
    9. 4.9  I2C Interface
    10. 4.10 Industrial Application LEDs
    11. 4.11 UART Interface
    12. 4.12 eQEP Interface
    13. 4.13 CAN Interface
    14. 4.14 FSI Interface
    15. 4.15 JTAG Emulation
    16. 4.16 Test Automation Interface
    17. 4.17 SPI Interface
  8. 5References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used in This Design
  9.   A E3 Design Changes
  10.   B Revision A Design Changes
  11.   Revision History

4.7 Ethernet Interface

Note: The PRU internal pinmux mapping provided in the TRM is part of the original hardware definition of the PRU. However, due to the flexibility provided by the IP and associated firmware configuraitons, this is not necessarily a hard requirement. The first PRU implementation for AM65x had the MII TX pins swapped during initial SoC integration and this convention was maintained for subsequent PRU revisions to enable firmware reuse. To make use of the SDK firmware, use the SYSCONFIG generated PRU pin mapping.

The LaunchPad supports two Ethernet PHYs that are terminated to RJ45 connectors with integrated magnetics for external communication.

GUID-20210719-CA0I-P27R-VTR5-WWDPL79WWQBQ-low.png Figure 4-9 Ethernet Connection

The 48 pin PHY (DP83869) is configured to advertise gigabit operation with the internal delay set to accommodate the internal delay of the AM243x SoC.

The first PHY is interfaced to the PRG1/CPSW RGMII2 ports of the SoC that are internally multiplexed in the SoC and the MDI interface from the same PHY is terminated to a RJ45 connector with integrated magnetics.

The second PHY is interfaced to the PRG1/CPSW RGMII1 ports of the SoC that are multiplexed using an external on-board MUX whose select line is be controlled from a GPIO (PRG_CPSW_RGMII1_MUX_SEL) of the SoC and the MDI interface from the same PHY is terminated to a RJ45 connector with integrated magnetics. A 1:2 mux (TS3DDR3812RUAR) is used to select between the PRG1 and CPSW RGMII1 ports.

GUID-20210719-CA0I-GB9B-BR5T-3T87SZFJW2G8-low.png Figure 4-10 CPSW or PRG RGMII1 Ethernet Data Mux

To select between the PRG and CPSW operation for both PHYs, the MDIO and MDC signals, which are internally multiplexed in the SoC, must be selected from each controller.

Two RJ45 connectors with integrated magnetics and status LEDs (7499111614A from Wurth) are used on the board for Ethernet 10Mb/100Mb/1Gb connectivity.