SPRUJ22C November   2021  – September 2024 AWR2944 , AWR2944P

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Key Features
    3. 1.3 What’s Included
      1. 1.3.1 Kit Contents
      2. 1.3.2 mmWave Out-of-Box (OOB) Demo
  6. 2Hardware
    1. 2.1  Block Diagram
    2. 2.2  PCB Handling Recommendations
    3. 2.3  Power Connections
    4. 2.4  Connectors
      1. 2.4.1 MIPI 60-Pin Connector (J19)
      2. 2.4.2 Debug Connector-60 pin (J7)
      3. 2.4.3 CAN-A Interface Connector (J3)
      4. 2.4.4 CAN-B Interface Connector (J2)
      5. 2.4.5 Ethernet Ports (J4 and J9)
        1. 2.4.5.1 ECOs to Enable the DP83TC812R (AWR2944EVM) or DP83TG720S (AWR2944PEVM) PHY
          1. 2.4.5.1.1 ECO needed to source 25MHz clock from AWR2944P to DP83TG720S
      6. 2.4.6 USB Connectors (J8, J10)
      7. 2.4.7 OSC_CLKOUT Connector (J14)
      8. 2.4.8 PMIC SPI Connector (J16) (DNP)
      9. 2.4.9 Voltage Rails Ripple Measurement Connectors (J1, J5) (DNP)
    5. 2.5  Antenna
    6. 2.6  PMIC
    7. 2.7  On-Board Sensors
    8. 2.8  PC Connection
      1. 2.8.1 XDS110 Interface
      2. 2.8.2 FTDI Interface
    9. 2.9  Connecting the AWR2944EVM/AWR2944PEVM to the DCA1000 EVM
    10. 2.10 Jumpers, Switches, and LEDs
      1. 2.10.1 Switches
      2. 2.10.2 Sense On Power (SOP) Jumpers (J17, J18, J20)
      3. 2.10.3 I2C Connections
      4. 2.10.4 Push Buttons
      5. 2.10.5 LEDs
  7. 3Software
    1. 3.1 Software, Development Tools, and Example Code
  8. 4Hardware Design Files
    1. 4.1 Design Files
  9. 5Compliance Information
    1. 5.1 Requirements for Operating in the EU and UK regions
  10. 6Additional Information
    1.     Trademarks
  11. 7Revision History

2.10.2 Sense On Power (SOP) Jumpers (J17, J18, J20)

The AWR2944EVM/AWR2944PEVM can be set to operate in different modes based on the state of the SOP [2:0] lines. These lines are sensed ONLY during boot up of the AWR2944 device. The state of the device is described in Table 2-12.

A closed jumper refers to a ‘1’ and open the jumper refers to a ‘0’ state of the SOP signal going to the AWR2944 device.

Note: The SOP[2:0] pins can also be controlled via the onboard FTDI. In this case, the FTDI settings override the jumper settings.
Table 2-12 SOP[0:2] Modes
Reference Usage Comments

J17 (SOP 2), J18 (SOP 1), J20 (SOP 0)

 SOP[2:0]

101 (SOP mode 5) = Flashing mode

001 (SOP mode 4) = Functional mode

000 (SOP mode 3) = Reserved

011 (SOP mode 2) = Development mode

010 (SOP mode 1) = Reserved
AWR2944EVM, AWR2944PEVM SOP Jumpers Figure 2-28 SOP Jumpers

Additionally, the SOP[4:3] signals defines the XTAL clock input as per the below configurations provided in Table 2-13.

Table 2-13 SOP[4:3] Modes
Reference Usage Comments

R303, R312 Populated.

R301,R309 unpopulated

 SOP[4:3] 00 = 40MHz (Default state)

R301, R312 Populated.

R303,R319 unpopulated

 01 = 45.1584MHz

R303, R309 Populated.

R301,R312 unpopulated

 10 = 49.152MHz

R301, R309 Populated.

R303,R312 unpopulated

11 = 50MHz