SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see OSPI Not Supported Features.
The OSPI module supports four SPI modes. These modes are defined through the OSPI_CONFIG_REG[1] SEL_CLK_POL_FLD and OSPI_CONFIG_REG[2] SEL_CLK_PHASE_FLD bits. The SEL_CLK_POL_FLD bit defines the clock polarity and the SEL_CLK_PHASE_FLD bit defines the data launch and data capture relation to the OSPI clock edges. Table 12-147 gives a brief description of these modes.
SPI Mode | SEL_CLK_POL_FLD | SEL_CLK_PHASE_FLD | Description | |
---|---|---|---|---|
0 | 0 | 0 | Clock inactive state: low | |
Data launch edge: clock falling edge | ||||
Data capture edge: clock rising edge | ||||
1 | 0 | 1 | Clock inactive state: low | |
Data launch edge: clock rising edge | ||||
Data capture edge: clock falling edge | ||||
2 | 1 | 0 | Clock inactive state: high | |
Data launch edge: clock rising edge | ||||
Data capture edge: clock falling edge | ||||
3 | 1 | 1 | Clock inactive state: high | |
Data launch edge: clock falling edge | ||||
Data capture edge: clock rising edge |
Octal flash devices provide DQS signal which allows source synchronous capture, but for Quad flash devices the OSPI module has a loopback mode. In this loopback mode the clock, looped back at board level, is used for registering the input data, and the edge used is same as the launch edge, thus giving a full cycle path (for more information, see Read Data Capture).