SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The PCIe subsystem includes the CP_INTD module to aggregate some of the PCIe controller signals into the subsystem interrupts indicated in Table 12-117. The interrupt aggregator takes both level and pulse signals from the PCIe core and produces the aggregated pulse interrupt outputs.
The aggregator also supports the End of Interrupt (EOI) feature. EOI can be used to re-trigger a pulse interrupt output, if a PCIe controller level signal is still asserted at the end of interrupt processing. The re-triggering of the the pulse interrupt can be achieved by writing the specified EOI vector value to the PCIE_USER_EOI_VECTOR register.
Aggregated Interrupt | CP_INTD Registers and Bits Mapping | EOI_VECTOR | PCIe Controller Signal | Description | |
---|---|---|---|---|---|
PCIE_INTD_ENABLE_REG_SYS_0 PCIE_INTD_ENABLE_CLR_REG_SYS_0 PCIE_INTD_STATUS_REG_SYS_0(1) | |||||
PCIE_DOWNSTREAM_PULSE | 0 | pcie_downstream_0 | 0 | down_pf0_intr | Downstream PF0 interrupt (EP mode only) |
1 | pcie_downstream_1 | down_pf1_intr | Downstream PF1 interrupt (EP mode only) | ||
2 | pcie_downstream_2 | down_pf2_intr | Downstream PF2 interrupt (EP mode only) | ||
3 | pcie_downstream_3 | down_pf3_intr | Downstream PF3 interrupt (EP mode only) | ||
4 | pcie_downstream_4 | down_pf4_intr | Downstream PF4 interrupt (EP mode only) | ||
5 | pcie_downstream_5 | down_pf5_intr | Downstream PF5 interrupt (EP mode only) | ||
- | 31-6 | Reserved | - | - | - |
Aggregated Interrupt | CP_INTD Registers and Bits Mapping | EOI_VECTOR | PCIe Controller Signal | Description | |
---|---|---|---|---|---|
PCIE_INTD_ENABLE_REG_SYS_1 PCIE_INTD_ENABLE_CLR_REG_SYS_1 PCIE_INTD_STATUS_REG_SYS_1 | |||||
PCIE_FLR_PULSE | 0 | pcie_flr_0 | 1 | flr0_in_progress | PF0 function-level reset (EP mode only) |
1 | pcie_flr_1 | flr1_in_progress | PF1 function-level reset (EP mode only) | ||
2 | pcie_flr_2 | flr2_in_progress | PF2 function-level reset (EP mode only) | ||
3 | pcie_flr_3 | flr3_in_progress | PF3 function-level reset (EP mode only) | ||
4 | pcie_flr_4 | flr4_in_progress | PF4 function-level reset (EP mode only) | ||
5 | pcie_flr_5 | flr5_in_progress | PF5 function-level reset (EP mode only) | ||
6 | pcie_flr_6 | vf0_flr_in_progress | VF0 function-level reset (EP mode only) | ||
7 | pcie_flr_7 | vf1_flr_in_progress | VF1 function-level reset (EP mode only) | ||
8 | pcie_flr_8 | vf2_flr_in_progress | VF2 function-level reset (EP mode only) | ||
9 | pcie_flr_9 | vf3_flr_in_progress | VF3 function-level reset (EP mode only) | ||
10 | pcie_flr_10 | vf4_flr_in_progress | VF4 function-level reset (EP mode only) | ||
11 | pcie_flr_11 | vf5_flr_in_progress | VF5 function-level reset (EP mode only) | ||
12 | pcie_flr_12 | vf6_flr_in_progress | VF6 function-level reset (EP mode only) | ||
13 | pcie_flr_13 | vf7_flr_in_progress | VF7 function-level reset (EP mode only) | ||
14 | pcie_flr_14 | vf8_flr_in_progress | VF8 function-level reset (EP mode only) | ||
15 | pcie_flr_15 | vf9_flr_in_progress | VF9 function-level reset (EP mode only) | ||
16 | pcie_flr_16 | vf10_flr_in_progress | VF10 function-level reset (EP mode only) | ||
17 | pcie_flr_17 | vf11_flr_in_progress | VF11 function-level reset (EP mode only) | ||
18 | pcie_flr_18 | vf12_flr_in_progress | VF12 function-level reset (EP mode only) | ||
19 | pcie_flr_19 | vf13_flr_in_progress | VF13 function-level reset (EP mode only) | ||
20 | pcie_flr_20 | vf14_flr_in_progress | VF14 function-level reset (EP mode only) | ||
21 | pcie_flr_21 | vf15_flr_in_progress | VF15 function-level reset (EP mode only) | ||
PCIE_LEGACY_PULSE | 22 | pcie_legacy_0 | 2 | int0 | Legacy interrupt A (RP mode only) |
23 | pcie_legacy_1 | int1 | Legacy interrupt B (RP mode only) | ||
24 | pcie_legacy_2 | int2 | Legacy interrupt C (RP mode only) | ||
25 | pcie_legacy_3 | int3 | Legacy interrupt D (RP mode only) | ||
PCIE_PWR_STATE_PULSE | 26 | pcie_pwr_state | 3 | power_state_change_interrupt | Power state change to D1 or D3 |
- | 31-27 | Reserved | - | - | - |
Aggregated Interrupt | CP_INTD Registers and Bits Mapping | EOI_VECTOR | PCIe Controller Signal | Description | |
---|---|---|---|---|---|
PCIE_INTD_ENABLE_REG_SYS_2 PCIE_INTD_ENABLE_CLR_REG_SYS_2 PCIE_INTD_STATUS_REG_SYS_2 PCIE_INTD_STATUS_CLR_REG_SYS_2 | |||||
PCIE_DPA_PULSE | 0 | pcie_dpa_0 | N/A(1) | dpa_intr0 | PF0 DPA power state change (EP mode only) |
1 | pcie_dpa_1 | dpa_intr1 | PF1 DPA power state change (EP mode only) | ||
2 | pcie_dpa_2 | dpa_intr2 | PF2 DPA power state change (EP mode only) | ||
3 | pcie_dpa_3 | dpa_intr3 | PF3 DPA power state change (EP mode only) | ||
4 | pcie_dpa_4 | dpa_intr4 | PF4 DPA power state change (EP mode only) | ||
5 | pcie_dpa_5 | dpa_intr5 | PF5 DPA power state change (EP mode only) | ||
PCIE_ERROR_PULSE | 6 | pcie_error_0 | N/A(1) | correctable_error | Correctable error |
7 | pcie_error_1 | non_fatal_error | Non-Fatal error | ||
8 | pcie_error_2 | fatal_error | Fatal error | ||
PCIE_HOT_RESET_PULSE | 9 | pcie_hot_reset | N/A(1) | hot_reset | Hot reset (EP mode only) |
PCIE_LINK_STATE_PULSE | 10 | pcie_link_state | N/A(1) | link_state | Link down reset |
PCIE_PTM_VALID_PULSE | 11 | pcie_ptm | N/A(1) | ptm_local_timer_valid | PTM local timer valid (EP mode only) |
- | 31-12 | Reserved | - | - | - |