SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Table 12-389 shows information on how to program the EDP PHY (SERDES).
| General Information | |
|---|---|
| Standards / links / lanes supported | Display port and embedded display port / 2 links / 1, 2, or 4 lanes per link |
| Reference clock information and setup | |
| External / internal reference clock selection | Set up external or internal reference clock. |
| Reference clock frequency selection | Set up the reference clock programming for the selected reference clock frequency |
| PLL and high speed clocking information and setup | |
| PLL 0, Mode 0 | Display port link 0. Note, if only link 1 is used, PLL 0 must be programmed in the same was as PLL 1. |
| PLL 0, Mode 1 | Unused |
| PLL 1, Mode 0 | Display port link 1. Note, if only link 0 is used, PLL 1 must be programmed in the same was as PLL 0. |
| PMA common full rate and data rate clocks | Unused |
| PMA transceiver full rate and data rate clocks | Full rate and data rate clocks are used as specified in the PMA spec table Clock rates for supported standards. |
| Top level pins | |
| PMA: cmn_pll0_mode_sel (Driven by PHY internal logic) | 1’b0 |
| PMA: cmn_pll1_mode_sel (Driven by PHY internal logic) | 1’b0 |
| PHY: phy_l{nn:00}_mode[1:0] | 2’b11 |
| PHY: phy_link_cfg_ln_{n:1} | 1’b0 for slave lanes of each link 1’b1 for the master lane of each link |
| PHY configuration specific registers | |
| SERDES register PHY_AUTO_CFG_SPDUP, bit-fields [1] PHY_PLL_CFG_1 and [0] PHY_PLL_CFG_0 | 16’h0000 for single DP link configuration 16’h0002 for 2 DP link configuration |
| Set PLL analog clock divider values | |
| SERDES register CMN_PDIAG_PLL0_CLK_SEL_M0__CMN_PDIAG_PLL0_CTRL_M0 | Link 0: Program it as described |
| SERDES register CMN_PDIAG_PLL1_CLK_SEL_M0__CMN_PDIAG_PLL1_CTRL_M0 | Link 1: Program it as described |
| Select analog high speed clock, and transceiver clock divider values | |
| SERDES register XCVR_DIAG_HSCLK_DIV__XCVR_DIAG_HSCLK_SEL_j, bits [15:0] Link 0 Link 1 | 16’h0000 16’h0001 |
| SERDES register XCVR_DIAG_HSCLK_DIV__XCVR_DIAG_HSCLK_SEL_j, bits [31:16] | Program it as described |
| Select digital PLL clock and data rate divider values | |
| SERDES register XCVR_DIAG_PLLDRC_CTRL__XCVR_DIAG_XDP_PWRI_STAT_j Link 0 Link 1 | 16’h0001 16’h0009 |
| Protocol specific setup | |
| Display port and embedded display | Program it as described |