SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
There are several schemas of memory protection employed inside of the processors. Table 6-8 and Table 6-9 describe the schema and arrangement. This describes what bits are protected, how they are protected, the behavior when an error is detected and what bits can be disturbed for ECC testing purposes. This also lists the RAM_ID associated with each memory to the corresponding ECC aggregator.
The key for the protection schemes is as follows:
Memory | Protection | Parity/ECC Granularity | RAM Arrangement | RAM_ID | Notes |
---|---|---|---|---|---|
L1 I-Cache Data | Parity | 1 parity bit / 16 bits of Instruction data | [71] – Parity of all odd bits of [63:32] and [67] | 0-5 | Parity error invalidates the offending cache line, force a fetch from the L2 cache on the next access. No aborts are generated, location of error is repored in the A72 CPUMERR register. |
[70] – Parity of all even bits of [63:32] and [66] | |||||
[69] – Parity of all odd bits of [31:0] and [65] | |||||
[68] – Parity of all even bits of [31:0] and [64] | |||||
L1 I-Cache Tag | Parity | 2 parity bits / 36 bits tag entry | [107] – Parity of all odd bits of [104:72] | 6-7 | Parity error invalidates the offending cache line, force a fetch from the L2 cache on the next access. No aborts are generated, location of error is repored in the A72 CPUMERR register. |
[71] – Parity of all odd bits of [68:36] | |||||
[35] – Parity of all odd bits of [32:0] | |||||
[106] – Parity of all even bits of [104:72] | |||||
[70] – Parity of all even bits of [68:36] | |||||
[34] – Parity of all even bits of [32:0] | |||||
[105], [69], [33] – Valid bit | |||||
[104:72], [68:36], [32:0] – Tag | |||||
L1 D-cache Data | ECC SECDED | 32-bit word | [155:149] – ECC | 8-15 | Single bit errors are corrected in the background and the line is removed from the cache as part of the correction process. No exception or interrupt is generated, but the A72 MERR register is updated to indicate a non-fatal error. Double bit errors are detected and an imprecise data abort is triggered and the line is evicted from the cache. |
[148:117] – Data | |||||
[116:110] – ECC | |||||
[109:78] – Data | |||||
[77:71] – ECC | |||||
[70:39] – Data | |||||
[38:32] – ECC | |||||
[31:0] – Data | |||||
L1 D-Cache Tag | ECC SECDED | Tag for a single cache line | [39-33] – ECC for [32:2] Tag and [1:0] State | 16-19 | Single bit errors are corrected in the background and the line is removed from the cache as part of the correction process. No exception or interrupt is generated, but the A72 MERR register is updated to indicate a nonfatal error. Double bit errors are detected and an imprecise data abort is triggered and the line is evicted from the cache. |
L2 TLB | Parity | [129] – Parity Bit | 20-23 | Error detection results in entry invalidated, new pagewalk to refetch. | |
[128:0] – TLB data |
Memory | Protection | RAM Arrangement | RAM_ID | Notes |
---|---|---|---|---|
L2 Tag | ECC SECDED | Odd way: [77:71] – ECC for [70:41] Tag and [40:39] State | 12-27 | Accesses resulting in an L2 cache hit, where a single-bit error is detected on the data array, the L2 memory system supports in-line ECC correction. Uncorrected data is forwarded to the requesting unit, and in parallel, the ECC circuitry checks for accuracy. If a single-bit error is detected, any uncorrected data returned within two cycles before the error indicator must be discarded. |
Even Way: [38:32] – ECC for [31:2] Tag and [1:0] State | ||||
L2 Data | ECC SECDED | [143:128] – ECC | 4-11 | Accesses resulting in an L2 cache hit, where a single-bit error is detected on the Data array, the L2 memory system supports in-line ECC correction. Uncorrected data is forwarded to the requesting unit, and in parallel, the ECC circuitry checks for accuracy. If a single-bit error is detected, any uncorrected data returned within two cycles before the error indicator must be discarded. |
[127:0] - Data | ||||
L2 Snoop Tag RAM | ECC SECDED | [79:73] – ECC for [72:42] Tag and [41:40] State | 0-3 | For single-bit ECC errors detected, the request is flushed from the L2 pipeline and is forced to reissue. The tag bank where the single-bit error occurred, performs a read-modify-write sequence to correct the single-bit error in the array. The request is then reissued. |
[39:33] – ECC for [32:2] Tag and [1:0] State | ||||
L2 Inclusion PLRU RAM | ECC SECDED | [38:32] – ECC for [30:16] PLRU and [15:0] Inclusion | 30-31 | For single-bit ECC errors detected, the request is flushed from the L2 pipeline and is forced to reissue. The tag bank where the single-bit error occurred, performs a read-modify-write sequence to correct the single-bit error in the array. The request is then reissued. |
L2 Dirty RAM | ECC SECDED | [47:44] – ECC | 28-29 | For single-bit ECC errors detected, the request is flushed from the L2 pipeline and is forced to reissue. The tag bank where the single-bit error occurred, performs a read-modify-write sequence to correct the single-bit error in the array. The request is then reissued. |
[43:40] – Page Attribute | ||||
[39:37] – ECC | ||||
[36] – Dirty bit | ||||
[35:32] – ECC | ||||
[31:28] – Page Attribute | ||||
[27:25] – ECC | ||||
[24] – Dirty bit | ||||
[23:20] – ECC | ||||
[19:16] – Page Attribute | ||||
[15:13] – ECC | ||||
[12] – Dirty bit | ||||
[11:8] – ECC | ||||
[7:4] – Page Attribute | ||||
[3:1] – ECC | ||||
[0] – Dirty bit |