SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
In compare block active mode, the output signals of both CPUs are compared, and any difference in the outputs is indicated by the compare error signal. Additionally, as indicated in Table 6-15, the self test error signal is also asserted.
The self test error signal is shared by both the CCMR5's CPU compare and inactivity monitor blocks.
Not all flops inside the R5F CPU(s) are initialized at reset. To avoid an erroneous CCMR5 compare error, the application software needs to ensure that the CPU registers of both CPUs are initialized with the same values before the registers are used. This is to ensure that the programmer’s model CPU registers of both CPU are initialized properly.