SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
GPIO Interrupts
All GPIO interrupts are mapped to a series of event multiplexing Interrupt Router (INTRTR) modules. These multiplexors allow any one of the available GPIO interrupts to be selected and passed on as an event to the various processor interrupt controllers and DMA controllers. Event selection is controlled through associated registers within each INTRTR.
The GPIO Bank interrupts represent a consolidation of all 16 GPIO interrupts associated with each bank. These are also selectable through the INTRTR event multiplexors and can be used to increase the total number of events available to a processor at the expense of full event granularity.
GPIO Multiplexing
The device has six instances of GPIO modules. The GPIO modules are integrated in two groups.
The corresponding groups I/O pins are multiplexed within each group modules.
The GPIO pins are grouped into banks (16 pins per bank and 9 banks per module), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 288 (2 group instances x (9 banks x 16 pins)) I/O pins. Because WKPU_GPIOu_[89:143] (u = 0, 1), and GPIOn_[66:143] (n = 0, 2, 4, 6) are reserved in this device, general purpose interface supports up to 155 I/O pins.
GPIO Virtualization
The GPIO module does not support virtualization. Therefore, two or more physical GPIO modules are instantiated within the MAIN and WKUP Domains to provide virtualization and/or isolation of GPIO control between safety-critical and non-safety-critical subsystems. The Device maps each GPIO signal from each GPIO Module in a Domain to the same pins, allowing any of the GPIO Modules in the Domain to control the pin via the VGPIO_SEL fields of the associated PADCONFIG registers. The GPIO interrupts/events are selected between the GPIO instances based on the same VGPIO_SEL fields. The bank interrupts from the GPIO instances are not multiplexed.
Enabling GPIO as a Wakeup Source
During Device DeepSleep power saving mode, the GPIO functional clock is powered down. This would prevent the WKUP_GPIO module from detecting transitions on GPIO pins to be used as wakeup from DeepSleep events. In order to prevent this issue, special clocking and vbus control are implemented as part of the WKUP_GPIO integration to allow GPIO transition to remain detectable.
A clock mux is provided to allow the GPIO VBUS_CLK to be switched to an on-chip clock source prior to gating of the standard clock source (MCU_SYSCLK0/8) and power-down of the off-chip HFOSC0 oscillator. This clock mux is controlled by WKUP_CTRL_MMR0 register bits. Because there is no asynchronous bridge between the WKUP_GPIO module and the WKUP CBASS, the module register may only be accessed when it is clocked using the synchronous MCU_SYSCLK0/8 clock source. Prior to switching the clock source to prepare for DeepSleep, all VBUS accesses to the WKUP_GPIO module must be blocked through the dedicated LPSC using a clock stop request. Note that when wakeup functionality for the WKUP_GPIO is enabled, (through a WKUP_CTRL_MMR bit), this clock stop request will not actually propagate to the WKUP_GPIO module (or stop its clock.) Instead, it will be fed back to the LPSC as a clock stop acknowledged. This will cause the associated WKUP_CBASS0 to route all future WKUP_GPIO register accesses to a null endpoint. The WKUP_GPIO LPSC must be maintained in CLKSTOP mode until MCU_SYSCLK0/8 is fully restored upon wakeup from DeepSleep and the WKUP_GPIO clock mux has finished switching back to the normal VBUS clock source.
The following are the steps required (expected to be performed by the SMS) to enable WKUP_GPIO wakeup events prior to DeepSleep entry:
Once in deep sleep mode, any GPIO transition (low to high or high to low) intended to cause a wakeup must be maintain at its new value for at least 2 of the selected functional clock (CLK_32K or CLK_12M_RC) maximum periods to ensure proper detection. (Note that process variance of the RC clocks must be taken into account). The detected event will be latched in the GPIO INSTAT register and the gpio_lvl_intr wakeup event sent to the SMS to trigger the wakeup FSM.
After wakeup, the SMS must restore the MCU_SYSCLK0/8 operation to allow the wakeup source event to be latched within the SMS. Once this is done the SMS may restore access to the WKUP_GPIO module by reversing the steps above:
The specific GPIO source(s) of the wakeup event may be determined by reading the GPIO INSTAT register and cleared by writing 1’s to the set bits of the same register.