SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The functional aspect of the WB pipeline scaler unit is identical to the VID pipeline scaler unit (see Section 12.6.3.8.5, DISPC VID Scaler Unit), except that the WB scaler is 8-bit only and takes only the 8 most significant bits of the data fed through. The WB scaler, similarly to the one in the video pipeline, can perform scaling in the native ARGB, YUV422, or YUV420 formats. The support for scaling in YUV formats allows a YUV source to be scaled through video and write-back scalers without chroma up and downsampling, if the output is to remain in the same format. In addition, the scaling capability of VID and WB pipelines can be combined to double the maximum rescaling factor (applicable for memory-to-memory operations only).
The downscaling capability is further reduced, if the pipeline is doing a format conversion where downsampling is inherent. When doing RGB/YUV422-to-YUV420 conversion in WB pipeline, the downsampling capability of WB scaler is reduced to:
The write-back window attributes of the WB pipeline can be configured in the following register bit-fields:
The WB pipeline supports input source cropping to allow a sub-frame capture by specifying the offset position and the size of the sub-frame. With the offset position parameters (POSY, POSX) set to (0,0) and the size prameters (SIZEY, SIZEX) set to the full size, no clipping should be applied. The software must make sure that the clipping parameters are set up correctly to avoid going over the WB input frame boundaries. Otherwise, the pipeline may lock up.
Table 12-346 list the register fields in the function of the coefficients for the VID horizontal scaler in the DSS0_WB_FIR_COEF_H0_0 to DSS0_WB_FIR_COEF_H0_8, and DSS0_WB_FIR_COEF_H12_0 to DSS0_WB_FIR_COEF_H12_15 registers.
Phases | Ch(2) | Ch(1) | Ch(0) | Ch(-1) | Ch(-2) |
---|---|---|---|---|---|
Signed coefficient [29-20] FIRHC2 bitfield | Signed coefficient [19-10] FIRHC1 bitfield | Unsigned central coefficient [9-0] FIRHC0 bitfield | Signed coefifcient [19-10] FIRHC1 bitfield | Signed coefficient [29-20] FIRHC2 bitfield | |
0 | DSS0_WB_FIR_COEF_H12_0 | DSS0_WB_FIR_COEF_H12_0 | DSS0_WB_FIR_COEF_H0_0 | DSS0_WB_FIR_COEF_H12_0 | DSS0_WB_FIR_COEF_H12_0 |
1 | DSS0_WB_FIR_COEF_H12_1 | DSS0_WB_FIR_COEF_H12_1 | DSS0_WB_FIR_COEF_H0_1 | DSS0_WB_FIR_COEF_H12_15 | DSS0_WB_FIR_COEF_H12_15 |
2 | DSS0_WB_FIR_COEF_H12_2 | DSS0_WB_FIR_COEF_H12_2 | DSS0_WB_FIR_COEF_H0_2 | DSS0_WB_FIR_COEF_H12_14 | DSS0_WB_FIR_COEF_H12_14 |
3 | DSS0_WB_FIR_COEF_H12_3 | DSS0_WB_FIR_COEF_H12_3 | DSS0_WB_FIR_COEF_H0_3 | DSS0_WB_FIR_COEF_H12_13 | DSS0_WB_FIR_COEF_H12_13 |
4 | DSS0_WB_FIR_COEF_H12_4 | DSS0_WB_FIR_COEF_H12_4 | DSS0_WB_FIR_COEF_H0_4 | DSS0_WB_FIR_COEF_H12_12 | DSS0_WB_FIR_COEF_H12_12 |
5 | DSS0_WB_FIR_COEF_H12_5 | DSS0_WB_FIR_COEF_H12_5 | DSS0_WB_FIR_COEF_H0_5 | DSS0_WB_FIR_COEF_H12_11 | DSS0_WB_FIR_COEF_H12_11 |
6 | DSS0_WB_FIR_COEF_H12_6 | DSS0_WB_FIR_COEF_H12_6 | DSS0_WB_FIR_COEF_H0_6 | DSS0_WB_FIR_COEF_H12_10 | DSS0_WB_FIR_COEF_H12_10 |
7 | DSS0_WB_FIR_COEF_H12_7 | DSS0_WB_FIR_COEF_H12_7 | DSS0_WB_FIR_COEF_H0_7 | DSS0_WB_FIR_COEF_H12_9 | DSS0_WB_FIR_COEF_H12_9 |
8 | DSS0_WB_FIR_COEF_H12_8 | DSS0_WB_FIR_COEF_H12_8 | DSS0_WB_FIR_COEF_H0_8 | DSS0_WB_FIR_COEF_H12_8 | DSS0_WB_FIR_COEF_H12_8 |
9 | DSS0_WB_FIR_COEF_H12_9 | DSS0_WB_FIR_COEF_H12_9 | DSS0_WB_FIR_COEF_H0_7 | DSS0_WB_FIR_COEF_H12_7 | DSS0_WB_FIR_COEF_H12_7 |
10 | DSS0_WB_FIR_COEF_H12_10 | DSS0_WB_FIR_COEF_H12_10 | DSS0_WB_FIR_COEF_H0_6 | DSS0_WB_FIR_COEF_H12_6 | DSS0_WB_FIR_COEF_H12_6 |
11 | DSS0_WB_FIR_COEF_H12_11 | DSS0_WB_FIR_COEF_H12_11 | DSS0_WB_FIR_COEF_H0_5 | DSS0_WB_FIR_COEF_H12_5 | DSS0_WB_FIR_COEF_H12_5 |
12 | DSS0_WB_FIR_COEF_H12_12 | DSS0_WB_FIR_COEF_H12_12 | DSS0_WB_FIR_COEF_H0_4 | DSS0_WB_FIR_COEF_H12_4 | DSS0_WB_FIR_COEF_H12_4 |
13 | DSS0_WB_FIR_COEF_H12_13 | DSS0_WB_FIR_COEF_H12_13 | DSS0_WB_FIR_COEF_H0_3 | DSS0_WB_FIR_COEF_H12_3 | DSS0_WB_FIR_COEF_H12_3 |
14 | DSS0_WB_FIR_COEF_H12_14 | DSS0_WB_FIR_COEF_H12_14 | DSS0_WB_FIR_COEF_H0_2 | DSS0_WB_FIR_COEF_H12_2 | DSS0_WB_FIR_COEF_H12_2 |
15 | DSS0_WB_FIR_COEF_H12_15 | DSS0_WB_FIR_COEF_H12_15 | DSS0_WB_FIR_COEF_H0_1 | DSS0_WB_FIR_COEF_H12_1 | DSS0_WB_FIR_COEF_H12_1 |
In Table 12-346, the cells without color are duplicated from the grey cells.
Similar table approach applies to the vertical scaler (registers DSS0_WB_FIR_COEF_V0_0 to DSS0_WB_FIR_COEF_V0_8, and DSS0_WB_FIR_COEF_V12_0 to DSS0_WB_FIR_COEF_V12_15 are used).
Similar table approach applies to the coefficients for Cb/Cr filtering in case of YUV format (registers DSS0_WB_FIR_COEF_H0_C_0 to DSS0_WB_FIR_COEF_H0_C_8, and DSS0_WB_FIR_COEF_H12_C_0 to DSS0_WB_FIR_COEF_H12_C_15, and DSS0_WB_FIR_COEF_V0_C_0 to DSS0_WB_FIR_COEF_V0_C_8 and DSS0_WB_FIR_COEF_V12_C_0 to DSS0_WB_FIR_COEF_V12_C_15 are used).
The WB scaler unit vertical and/or horizontal sampling is selected by configuring the DSS0_WB_ATTRIBUTES[8-7] RESIZEENABLE register bit field.
Prior to enabling the WB scaler a valid configuration has to be set by the user.
In case of capturing data of one of the output channels, the corresponding DSS0_VP_CONTROL[5] GOBIT bit has to be set to update the configuration depending to which VP output the write-back pipeline is associated with. Refers also to Section 12.6.3.15, DISPC Shadow Mechanism for Registers when write back channel is active. The SW has to wait before setting the GOBIT bit that the HW has reset the same bit. The DSS0_WB_ATTRIBUTES[0] ENABLE bit can be set to update those registers, if it has been previously disabled.
The following register fields define the configuration of the video up/downsampling block in the WB pipeline:
Table 12-347 lists the DISPC vertical and horizontal accumulator values and phases. Other accumulator values are also supported. The HW determines the nearest phase value in order to load the corresponding one.
Accumulator Value (MSB bits) | Phases f |
---|---|
0 | 0 |
256 or -3840 | 1 |
512 or -3584 | 2 |
768 or -3328 | 3 |
1024 or -3072 | 4 |
1280 or -2816 | 5 |
1536 or -2560 | 6 |
1792 or -2304 | 7 |
2048 or -2048 | 8 |
2304 or -1792 | 9 |
2560 or -1536 | 10 |
2816 or -1280 | 11 |
3072 or -1024 | 12 |
3328 or -768 | 13 |
3584 or -512 | 14 |
3840 or -256 | 15 |
The YUV filtering is based on the equations of the ARGB filtering. In addition to the registers used for ARGB filtering configuration, a second set of registers for filtering is used. The first set of registers is used for Y configuration (instead of ARGB configuration) and the second set of registers is used for CbCr filtering configuration. The two sets of registers can be the same when the YUV format is not converted to RGB after filtering. When the RGB conversion is required after filtering, then the chrominance needs to be re-sampled with a different filtering configuration because: