SPRUJ28 User guide

SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

12.6.3.9.2 DISPC WB Scaler Unit

The functional aspect of the WB pipeline scaler unit is identical to the VID pipeline scaler unit (see Section 12.6.3.8.5, DISPC VID Scaler Unit), except that the WB scaler is 8-bit only and takes only the 8 most significant bits of the data fed through. The WB scaler, similarly to the one in the video pipeline, can perform scaling in the native ARGB, YUV422, or YUV420 formats. The support for scaling in YUV formats allows a YUV source to be scaled through video and write-back scalers without chroma up and downsampling, if the output is to remain in the same format. In addition, the scaling capability of VID and WB pipelines can be combined to double the maximum rescaling factor (applicable for memory-to-memory operations only).

The downscaling capability is further reduced, if the pipeline is doing a format conversion where downsampling is inherent. When doing RGB/YUV422-to-YUV420 conversion in WB pipeline, the downsampling capability of WB scaler is reduced to:

If 5 taps is selected, then the downsampling is limited to 0.5 in RGB
If 3 taps is selected, then no down-scaling is available

The write-back window attributes of the WB pipeline can be configured in the following register bit-fields:

Source data format for write-back (input to the scaler unit) in DSS0_WB_ATTRIBUTES[6-1] FORMAT bit-field
Start position (offset) of the window on the overlay which WB will capture in DSS0_WB_POSITION[29-16] POSY and [13-0] POSX register field. Only applicable when the WB pipeline is operating in capture_mode.
Write-back picture width in system memory (frame buffer) in DSS0_WB_PICTURE_SIZE[13-0] MEMSIZEX bit-field. The window width is from 1 up to 4096 pixels. All the integer values in the range [1:4096] are allowed in the case of RGB16 and RGB24 video data. In the case of YUV2422 and UYVY422 formats the width has to be a multiple of 2 pixels.
Write-back picture height in system memory (frame buffer) in DSS0_WB_PICTURE_SIZE[29-16] MEMSIZEY bit-field. The window width is from 1 up to 4096 pixels. All the integer values in the range [1:4096] are allowed. In the case of YUV420 the height has to be a multiple of 2 lines.
Write-back window width at pipeline input (before resizing) in DSS0_WB_SIZE[13-0] SIZEX bit-field. The window width is from 1 up to 4096 pixels. The width of the image sent to the write back pipe has to be a multiple of 2 pixels, if its format (input) is YUV420/YUV422.
Write-back window height at pipeline input (before resizing) in DSS0_WB_SIZE[29-16] SIZEY bit-field. The window height is from 1 up to 4096 pixels. The width of the image sent to the write back pipe has to be a multiple of 2 lines, if its format (input) is YUV420.

Note:

The WB pipeline supports input source cropping to allow a sub-frame capture by specifying the offset position and the size of the sub-frame. With the offset position parameters (POSY, POSX) set to (0,0) and the size prameters (SIZEY, SIZEX) set to the full size, no clipping should be applied. The software must make sure that the clipping parameters are set up correctly to avoid going over the WB input frame boundaries. Otherwise, the pipeline may lock up.

Table 12-346 list the register fields in the function of the coefficients for the VID horizontal scaler in the DSS0_WB_FIR_COEF_H0_0 to DSS0_WB_FIR_COEF_H0_8, and DSS0_WB_FIR_COEF_H12_0 to DSS0_WB_FIR_COEF_H12_15 registers.

Table 12-346 DISPC Register Fields Associated to Coefficients for ARGB and Y Configuration in WB Horizontal Scaler

Phases	Ch(2)	Ch(1)	Ch(0)	Ch(-1)	Ch(-2)
	Signed coefficient [29-20] FIRHC2 bitfield	Signed coefficient [19-10] FIRHC1 bitfield	Unsigned central coefficient [9-0] FIRHC0 bitfield	Signed coefifcient [19-10] FIRHC1 bitfield	Signed coefficient [29-20] FIRHC2 bitfield
0	DSS0_WB_FIR_COEF_H12_0	DSS0_WB_FIR_COEF_H12_0	DSS0_WB_FIR_COEF_H0_0	DSS0_WB_FIR_COEF_H12_0	DSS0_WB_FIR_COEF_H12_0
1	DSS0_WB_FIR_COEF_H12_1	DSS0_WB_FIR_COEF_H12_1	DSS0_WB_FIR_COEF_H0_1	DSS0_WB_FIR_COEF_H12_15	DSS0_WB_FIR_COEF_H12_15
2	DSS0_WB_FIR_COEF_H12_2	DSS0_WB_FIR_COEF_H12_2	DSS0_WB_FIR_COEF_H0_2	DSS0_WB_FIR_COEF_H12_14	DSS0_WB_FIR_COEF_H12_14
3	DSS0_WB_FIR_COEF_H12_3	DSS0_WB_FIR_COEF_H12_3	DSS0_WB_FIR_COEF_H0_3	DSS0_WB_FIR_COEF_H12_13	DSS0_WB_FIR_COEF_H12_13
4	DSS0_WB_FIR_COEF_H12_4	DSS0_WB_FIR_COEF_H12_4	DSS0_WB_FIR_COEF_H0_4	DSS0_WB_FIR_COEF_H12_12	DSS0_WB_FIR_COEF_H12_12
5	DSS0_WB_FIR_COEF_H12_5	DSS0_WB_FIR_COEF_H12_5	DSS0_WB_FIR_COEF_H0_5	DSS0_WB_FIR_COEF_H12_11	DSS0_WB_FIR_COEF_H12_11
6	DSS0_WB_FIR_COEF_H12_6	DSS0_WB_FIR_COEF_H12_6	DSS0_WB_FIR_COEF_H0_6	DSS0_WB_FIR_COEF_H12_10	DSS0_WB_FIR_COEF_H12_10
7	DSS0_WB_FIR_COEF_H12_7	DSS0_WB_FIR_COEF_H12_7	DSS0_WB_FIR_COEF_H0_7	DSS0_WB_FIR_COEF_H12_9	DSS0_WB_FIR_COEF_H12_9
8	DSS0_WB_FIR_COEF_H12_8	DSS0_WB_FIR_COEF_H12_8	DSS0_WB_FIR_COEF_H0_8	DSS0_WB_FIR_COEF_H12_8	DSS0_WB_FIR_COEF_H12_8
9	DSS0_WB_FIR_COEF_H12_9	DSS0_WB_FIR_COEF_H12_9	DSS0_WB_FIR_COEF_H0_7	DSS0_WB_FIR_COEF_H12_7	DSS0_WB_FIR_COEF_H12_7
10	DSS0_WB_FIR_COEF_H12_10	DSS0_WB_FIR_COEF_H12_10	DSS0_WB_FIR_COEF_H0_6	DSS0_WB_FIR_COEF_H12_6	DSS0_WB_FIR_COEF_H12_6
11	DSS0_WB_FIR_COEF_H12_11	DSS0_WB_FIR_COEF_H12_11	DSS0_WB_FIR_COEF_H0_5	DSS0_WB_FIR_COEF_H12_5	DSS0_WB_FIR_COEF_H12_5
12	DSS0_WB_FIR_COEF_H12_12	DSS0_WB_FIR_COEF_H12_12	DSS0_WB_FIR_COEF_H0_4	DSS0_WB_FIR_COEF_H12_4	DSS0_WB_FIR_COEF_H12_4
13	DSS0_WB_FIR_COEF_H12_13	DSS0_WB_FIR_COEF_H12_13	DSS0_WB_FIR_COEF_H0_3	DSS0_WB_FIR_COEF_H12_3	DSS0_WB_FIR_COEF_H12_3
14	DSS0_WB_FIR_COEF_H12_14	DSS0_WB_FIR_COEF_H12_14	DSS0_WB_FIR_COEF_H0_2	DSS0_WB_FIR_COEF_H12_2	DSS0_WB_FIR_COEF_H12_2
15	DSS0_WB_FIR_COEF_H12_15	DSS0_WB_FIR_COEF_H12_15	DSS0_WB_FIR_COEF_H0_1	DSS0_WB_FIR_COEF_H12_1	DSS0_WB_FIR_COEF_H12_1

Note:

In Table 12-346, the cells without color are duplicated from the grey cells.

Similar table approach applies to the vertical scaler (registers DSS0_WB_FIR_COEF_V0_0 to DSS0_WB_FIR_COEF_V0_8, and DSS0_WB_FIR_COEF_V12_0 to DSS0_WB_FIR_COEF_V12_15 are used).

Similar table approach applies to the coefficients for Cb/Cr filtering in case of YUV format (registers DSS0_WB_FIR_COEF_H0_C_0 to DSS0_WB_FIR_COEF_H0_C_8, and DSS0_WB_FIR_COEF_H12_C_0 to DSS0_WB_FIR_COEF_H12_C_15, and DSS0_WB_FIR_COEF_V0_C_0 to DSS0_WB_FIR_COEF_V0_C_8 and DSS0_WB_FIR_COEF_V12_C_0 to DSS0_WB_FIR_COEF_V12_C_15 are used).

The WB scaler unit vertical and/or horizontal sampling is selected by configuring the DSS0_WB_ATTRIBUTES[8-7] RESIZEENABLE register bit field.

Prior to enabling the WB scaler a valid configuration has to be set by the user.

In case of capturing data of one of the output channels, the corresponding DSS0_VP_CONTROL[5] GOBIT bit has to be set to update the configuration depending to which VP output the write-back pipeline is associated with. Refers also to Section 12.6.3.15, DISPC Shadow Mechanism for Registers when write back channel is active. The SW has to wait before setting the GOBIT bit that the HW has reset the same bit. The DSS0_WB_ATTRIBUTES[0] ENABLE bit can be set to update those registers, if it has been previously disabled.

The following register fields define the configuration of the video up/downsampling block in the WB pipeline:

Vertical up/downsampling increment value in the[23-0] FIRVINC bit field of DSS0_WB_FIRV (for ARGB and Y) and DSS0_WB_FIRV2 (for CbCr) registers. Software calculates the value using the following equation:
Equation 25.
Horizontal up/downsampling increment value in the [23-0] FIRHINC bit field of the DSS0_WB_FIRH (for ARGB and Y) and DSS0_WB_FIRH2 (for CbCr) registers. Software calculates the value using the following equation:
Equation 26.
Vertical up/downsampling accumulator value in the [23-0] VERTICALACCU bit field of the DSS0_WB_ACCUV_0 and DSS0_WB_ACCUV_1 (for ARGB and Y), and DSS0_WB_ACCUV2_0 and DSS0_WB_ACCUV2_1 (for CbCr) registers. The accumulator value indicates on which phase the vertical filtering starts.
Vertical upsampling and downsampling line buffer configuration via the DSS0_WB_ATTRIBUTES[21] VERTICALTAPS bit. The default value at reset time is 0x0 (3-tap configuration is used). If the bit field is reset, the 3-tap configuration is used.
Horizontal upsampling and downsampling accumulator value in the [23-0] HORIZONTALACCU bit field of the DSS0_WB_ACCUH_0 and DSS0_WB_ACCUH_1 (for ARGB and Y), and DSS0_WB_ACCUH2_0 and DSS0_WB_ACCUH2_1 (for CbCr) registers. The accumulator value indicates on which phase the horizontal filtering starts.

Table 12-347 lists the DISPC vertical and horizontal accumulator values and phases. Other accumulator values are also supported. The HW determines the nearest phase value in order to load the corresponding one.

Table 12-347 DISPC WB Scaler Vertical and Horizontal Accumulator Phases

Accumulator Value (MSB bits)	Phases f
0	0
256 or -3840	1
512 or -3584	2
768 or -3328	3
1024 or -3072	4
1280 or -2816	5
1536 or -2560	6
1792 or -2304	7
2048 or -2048	8
2304 or -1792	9
2560 or -1536	10
2816 or -1280	11
3072 or -1024	12
3328 or -768	13
3584 or -512	14
3840 or -256	15

Vertical upsampling and downsampling central coefficients:
- For ARGB and Y, the vertical upsampling and downsampling central coefficients are defined in the DSS0_WB_FIR_COEF_V0_0 to DSS0_WB_FIR_COEF_V0_8 registers. There are 9 registers for the 16 phases with 1 coefficient for each of them. Symetrical implementation is used, so only 9 coefficients are used. Each register contains one 10-bit unsigned coefficient (the central one).
- Four CbCr, the vertical upsampling and downsampling central coefficients are set in DSS0_WB_FIR_COEF_V0_C_0 to DSS0_WB_FIR_COEF_V0_C_8 registers.
Vertical upsampling and downsampling coefficients:
- For ARGB and Y, the vertical upsampling and downsampling coefficients are defined in the DSS0_WB_FIR_COEF_V12_0 to DSS0_WB_FIR_COEF_V12_15 registers. There are 16 registers for the 16 phases with 2 coefficient for each of them, so a total of 32 programmable coefficients for the vertical up/down-sampling block. Each register contains two 10-bit signed coefficients.
- Four CbCr, the vertical upsampling and downsampling coefficients are set in DSS0_WB_FIR_COEF_V12_C_0 to DSS0_WB_FIR_COEF_V12_C_15 registers.
Horizontal upsampling and downsampling central coefficients:
- For ARGB and Y, the horizontal upsampling and downsampling central coefficients are defined in the DSS0_WB_FIR_COEF_H0_0 to DSS0_WB_FIR_COEF_H0_8 registers. There are 9 registers for the 16 phases with 1 coefficient for each of them. Symetrical implementation is used, so only 9 coefficients are used. Each register contains one 10-bit unsigned coefficient (the central one).
- Four CbCr, the horizontal upsampling and downsampling central coefficients are set in DSS0_WB_FIR_COEF_H0_C_0 to DSS0_WB_FIR_COEF_H0_C_8 registers.
Horizontal upsampling and downsampling coefficients:
- For ARGB and Y, the horizontal upsampling and downsampling coefficients are defined in the DSS0_WB_FIR_COEF_H12_0 to DSS0_WB_FIR_COEF_H12_15 registers. There are 16 registers for the 16 phases with 2 coefficient for each of them, so a total of 32 programmable coefficients for the horizontal up/down-sampling block. Each register contains two 10-bit signed coefficients.
- Four CbCr, the horizontal upsampling and downsampling coefficients are set in DSS0_WB_FIR_COEF_H12_C_0 to DSS0_WB_FIR_COEF_H12_C_15 registers.

The YUV filtering is based on the equations of the ARGB filtering. In addition to the registers used for ARGB filtering configuration, a second set of registers for filtering is used. The first set of registers is used for Y configuration (instead of ARGB configuration) and the second set of registers is used for CbCr filtering configuration. The two sets of registers can be the same when the YUV format is not converted to RGB after filtering. When the RGB conversion is required after filtering, then the chrominance needs to be re-sampled with a different filtering configuration because:

Chrominance samples are offset to the luminance samples. That is, DSS0_WB_FIRH2 and DSS0_WB_FIRV2, and DSS0_WB_ACCUV2_0/DSS0_WB_ACCUV2_1 and DSS0_WB_ACCUH2_0/DSS0_WB_ACCUH2_1 registers need to be configured differently than DSS0_WB_FIRH and DSS0_WB_FIRV, and DSS0_WB_ACCUH_0/DSS0_WB_ACCUH_1 and DSS0_WB_ACCUV_0/DSS0_WB_ACCUV_1 registers used for the luminance filtering.
Chrominance is sub-sampled by two horizontally only in case of YUV422, and horizontally and vertically in case of YUV420. The coefficients for the vertical chrominance re-sampling are identical to the coefficients for vertical luminance filtering in case of YUV422. The coefficients for the horizontal and vertical chrominance re-sampling are different than the ones for luminance filtering in case of YUV420.