SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
This section describes the DDRSS0 external connections (environment).
Table 8-14 describes the DDRSS0 I/O signals used for connection to SDRAM devices.
Module Pin | I/O(1) | Description |
---|---|---|
RSTN | I/O | SDRAM reset |
CKE[1-0] | I/O | SDRAM CKE[1-0] signals |
CK | I/O | SDRAM differential clock pair |
CKN | ||
CSN0_0 | I/O | SDRAM chip select 0 (two copies of CS0)(2) |
CSN0_1 | ||
CSN1_0 | I/O | SDRAM chip select 1 (two copies of CS1)(2) |
CSN1_1 | ||
CA[5-0] | I/O | SDRAM address and command bus |
DQS[3-0] | I/O | SDRAM data strobe |
DQSN[3-0] | I/O | SDRAM data strobe invert |
DQ[31-0] | I/O | SDRAM data bus |
DM[3-0] | I/O | SDRAM data mask/DBI |
RET | I/O | External I/O retention enable |
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.