OSPI module fully integrates PHY module dedicated to more flexible and power efficient transfers.
The PHY module communicates with the OSPI Flash controller via the aforementioned PHY Interface and handles data transfer on low-level stage of design hierarchy. However, when the OSPI_RCLK is configured to be equal to the SPI clock instead of alternative approach using clock divider, there is just one OSPI_RCLK cycle (not 4 or more) within single SPI period or half period for DDR Mode (SPI Control Module works on reference clock). Given that OSPI_RCLK is the input clock for RX FIFO and the output one for TX FIFO, the PHY solution incurs more restrictive requirement for value of system clock in order to synchronize data without SPI transfer interruption. For example, when the controller operates in DDR 1× octal Mode, 2 bytes of data (equivalent to one RX FIFO location) is gathered within just single OSPI_RCLK cycle. The controller cannot predict next data access while operating in the Direct Mode (meaning its size or whether it is sequential to the previous one or not). As a result, if the OSPI_HCLK is not significantly greater than OSPI_RCLK, the SPI transfer has to be suspended until the Flash Command Generator forwards new data to TX FIFO.
An optional PHY Pipeline Mode is implemented to avoid the necessity of stable clocking of the system clock for the Direct Mode when the PHY mode is enabled and to keep maximum performance while ensuring correct operation of the OSPI controller with the PHY using low frequencies from all its domains. This mode is a trade-off between large software overhead when operating in the Indirect Mode and the described limitations present in the Direct Mode. For more information about PHY Pipeline Mode, see Section 12.3.2.3.16.1, PHY Pipeline Mode.
When DDR 2× Mode is granted based on configuration
– SPI transfer is automatically performed using the PHY module even if the
OSPI_CONFIG_REG[3] PHY_MODE_ENABLE_FLD is de-asserted. SDR 2× commands are handled
with PHY module paths being bypassed. Nevertheless, dividers of 2, 4 or 6 for DDR
and divider of 2 for SDR should not be configured based on controller requirements
and these configurations are perceived as a software error.
The following steps are an example of software algorithm of adapting the OSPI controller with the PHY module incorporated to work in octal 1× clock DDR Protocol. Note that all necessary configuration steps described in Section 12.3.2.4.2, Configuring the OSPI Controller for Optimal Use shall be completed before the algorithm.
- Set PHY mode enable (OSPI_CONFIG_REG[3]
PHY_MODE_ENABLE_FLD bit) and DDR protocol (OSPI_CONFIG_REG[24]
ENABLE_DTR_PROTOCOL_FLD bit). It is assumed that device is configured to
work in DDR Protocol.
- Before setting the DLL parameters, software
calibration could be needed.
OSPI_PHY_MASTER_CONTROL_REG[23] PHY_MASTER_BYPASS_MODE_FLD bit controls
the bypass mode of the master and slave DLLs. If this bit is set, the DLL
bypass mode is enabled. This mode is intended to be used only for debug.
When set to 0, a Master operational mode is selected, when set to 1 the
Bypass mode is selected.
DLL works in normal
mode of operation where the slave delay line settings are used as fractional
delay of the master delay line encoder reading of the number of delays in
one cycle.
Master DLL is disabled with only 1
delay element in its delay line. The slave delay lines decode delays in
absolute delay elements rather than as fractional delays.
- DLL Bypass Mode
(follow only if operating in this mode):
- Depending on
frequency of reference clock, calculate how many delay
elements should be used to shift this clock by 25% of its
period (best case for DDR transfers from setup/hold timings
standpoint). Note that delay could be slightly different in
a real design. TX Delay is configured in
OSPI_PHY_CONFIGURATION_REG[22-16]
PHY_CONFIG_TX_DLL_DELAY_FLD bit field.
- Re-synchronize DLLs by asserting
OSPI_PHY_CONFIGURATION_REG[31] PHY_CONFIG_RESYNC_FLD bit (If
this bit is already set by previous re-synchronization,
toggle sequence from "0" to "1" must be generated in order
to trigger re-synchronization DLL logic) and set PHY bypass
mode enable through OSPI_PHY_MASTER_CONTROL_REG[23]
PHY_MASTER_BYPASS_MODE_FLD bit.
- DLL Master Mode
(follow only if operating in this mode):
- Drive DLL
reset bit OSPI_PHY_CONFIGURATION_REG[30]
PHY_CONFIG_RESET_FLD into low.
- Calculate
initial delay value for the Master DLL according to the
OSPI_PHY_MASTER_CONTROL_REG[6-0]
PHY_MASTER_INITIAL_DELAY_FLD bit field.
- Depending on
frequency of reference clock, calculate how many delay
elements should be used to shift this clock by 25% of its
period (best case for DDR transfers from setup/hold timings
standpoint). Note that delay could be slightly different in
a real design. TX Delay is configured in
OSPI_PHY_CONFIGURATION_REG[22-16]
PHY_CONFIG_TX_DLL_DELAY_FLD bit field.
- Re-synchronize DLLs by asserting
OSPI_PHY_CONFIGURATION_REG[31] PHY_CONFIG_RESYNC_FLD (If
this bit is already set by previous re-synchronization,
toggle sequence from "0" to "1" must be generated in order
to trigger re-synchronization DLL logic) and set DLL reset
bit back to high (since both bits are within the same
register, it is acceptable to set both bits
simultaneously).
- Poll
OSPI_DLL_OBSERVABLE_LOWER_REG[15]
DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD bit. When set – lock
is done.
- Re-synchronize Slave DLLs by asserting
OSPI_PHY_CONFIGURATION_REG[31] PHY_CONFIG_RESYNC_FLD bit (If
this bit is already set by previous re-synchronization,
toggle sequence from "0" to "1" must be generated in order
to trigger re-synchronization DLL logic) and set TX DLL
Delay (OSPI_PHY_CONFIGURATION_REG[22-16]
PHY_CONFIG_TX_DLL_DELAY_FLD) and RX DLL Delay
(OSPI_PHY_CONFIGURATION_REG[6-0]
PHY_CONFIG_RX_DLL_DELAY_FLD) fields which are equivalent to
percentage clock offsets now. It is recommended to wait for
the new configuration being propagated by 20 reference clock
cycles before triggering the next SPI transfer.
- Consider Read Data
from location where its value is predictable. This step can be
performed in different ways, depending on the device. Parameter
Page, ID, Status, Data from OTP region or Data from location of
Flash Array the value of which is known can act as the pattern.
- Trigger Read request
chosen from above options.
- Check correctness of
data and store that information:
- Increment value of RX clock delay – it
is configurable in the OSPI_PHY_CONFIGURATION_REG[6-0]
PHY_CONFIG_RX_DLL_DELAY_FLD bit field.
-
Re-synchronize DLLs.
- Trigger valid
Read request.
- Check
correctness of data and store information.
- If range
boundary of RX clock delay is achieved, go to step 3.
Otherwise go back to step "Increment value of RX clock
delay".
- Set RX clock delay value for one from the middle of valid range based on information in storage.
- Re-synchronize DLLs.
- Set OSPI_DEV_INSTR_RD_CONFIG_REG for Octal Read
DDR Configuration (each transfer phase should be configured to work in Octal
mode, Number of Dummy cycles should be set as specified in the documentation
of the device or more when because of additional read paths delays of actual
systems data is predicted to be flopped by PHY module with delay excesses
actual cycle of SPI clock generated by the controller).
- Enable Pipeline mode in the OSPI_CONFIG_REG[25]
PIPELINE_PHY_FLD bit.
- Perform Sequential Read of Data consistent with conditions indicated within Section 12.3.2.3.16.1, PHY Pipeline Mode.
- After de-asserting the data slave select signal by software – poll
OSPI_CONFIG_REG[31] IDLE_FLD bit.
- When it is asserted to high – next transfer request can be triggered.