SerDes' goal is to convert device (SoC) parallel
data into serialized data that can be output over a high-speed electrical interface.
In the opposite direction, SerDes converts high-speed serial data into parallel data
that can be processed by the device. To this end, the SerDes contains a variety of
functional blocks to handle both the external analog interface as well as the
internal digital logic.
Most important building blocks of SerDes are:
- Physical Media Attachment (PMA):
- Lanes: The lanes handle all inputs and outputs from the serial interface, and contain the Tx/Rx I/Os, serializer/deserializer, and Clock and Data Recovery (CDR) unit.
- Common module (CMN): The CMN handles peripheral and Tx clocking of the SerDes. It consists of internal PLLs and external reference clock input buffer, reset, and startup circuitry.
- Physical Coding Sub-block (PCS): The PCS is responsible for translating data from/to the parallel interface, as well as data encoding/decoding and symbol alignment.
- WIZ: The WIZ acts as a wrapper for the SerDes, and can both send control signals to and report status signals from the SerDes, and muxes SerDes to peripherals.