SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Figure 1-1 shows the initial setup for interrupt-based transmission.
Table 12-316 shows the configuration of the MCASP using an interrupt method for DIT-/TDM- transmission.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Disable Tx DMA requests generation. | MCASP_XEVTCTL[0] XDATDMA | 0x1 |
Enable the data ready event transmit interrupt. | MCASP_XINTCTL[5] XDATA | 0x1 |
Optional: Enable the transmit error event interrupts. | MCASP_XINTCTL[2] XCKFAIL MCASP_XINTCTL[1] XSYNCERR MCASP_XINTCTL[0] XUNDRN | 0x1 0x1 0x1 |
Optional: Enable the start of frame interrupt. Optional: Enable the last slot data interrupt (useful for DIT user data/ channel status next S/PDIF frame info update). | MCASP_XINTCTL[7] XSTAFRM MCASP_XINTCTL[4] XLAST | 0x1 0x1 |
IFwrite transfer is through the MCASP DATA port (MCASP_XFMT[3] XBUSEL is set to 0b0). | Software test condition (setting is done in step4 of the MCASP Transmitters Global Initialization - see MCASP Transmitters Global Initialization for DIT-Mode Operation) | |
Enable the DATA port error based interrupt. | MCASP_XINTCTL[3] XDMAERR | 0x1 |
ELSE | ||
Disable the DATA port error based interrupt. | MCASP_XINTCTL[3] XDMAERR | 0x0 |
ENDIF | ||
DIT/TDM - Transmission Startup Procedure | See Figure 12-282. |
These registers are for MCASP DIT-/TDM- transmission startup procedure: MCASP_GBLCTL, MCASP_XSTAT.