The FSS provides access to external Flash and RAM devices. It supports XIP (Execute-in-Place) and BC (Block Copy) operations.
The FSS consists of two OSPIs and one HyperBus interface. There are two FSS paths - FSS0 and FSS1 (see ). The first path (FSS0) includes OSPI0 and HyperBus interface. The second path (FSS1) includes OSPI1. These two FSS paths can be used simultaneously (see FSS Typical Application).
Table 12-142 shows the FSS allowed interface combinations.
Table 12-142 FSS Allowed Interface Combinations
Combination |
Primary Interface (FSS0) |
Secondary Interface (FSS1) |
1. |
OSPI0 (MCU_FSS0_OSPI0) |
Not Used |
2. |
HyperBus Interface (MCU_FSS0_HPB0) |
Not Used |
3. |
OSPI0 (MCU_FSS0_OSPI0) |
OSPI1 (MCU_FSS0_OSPI1) |
4. |
HyperBus Interface (MCU_FSS0_HPB0) |
OSPI1 (MCU_FSS0_OSPI1) |
5. |
Not Used |
OSPI1 (MCU_FSS0_OSPI1) |
Figure 12-72 shows the FSS block diagram.
FSS Blocks:
- MCU_CBASS0: The MCU_CBASS0 interconnect allows FSS to communicate with the device modules and subsystems.
- Data Interface (FSS0): It is 64-bit data/32-bit address multi issue data interface with coherent in-band bypass. It provides accessibility to either the OSPI0 or HyperBus interface.
- Data Interface (FSS1): It is 64-bit data/32-bit address multi issue data interface with coherent in-band bypass. It provides accessibility to the OSPI1.
- Config Interface: It is used for configuration of the memory mapped registers within the FSS.
- Interface Clock and Reset:
- For more information, see MCU_FSS0 Clocks and Resets.
- For more information, see MCU_FSS0_OSPI Clocks and Resets.
- For more information, see MCU_FSS0_HPB0 Clocks and Resets.
- Memory Mapped Registers: This block conditionally includes registers from the following blocks: FSS, ECC, MUX, and DF. The configuration of these registers defines which combination of FSS interfaces is selected (see Table 12-142) and also which FSS features and operation modes are used. For more information, see MCU_FSS0_SYSCONFIG.
- MUX: The Muxing (MUX) block is used as a software controlled switch in the primary FSS (FSS0) interface. It defines which interface to be used (OSPI0 or HyperBus interface). The MUX block can switch only when the traffic is idle. The software has responsibility to cause the traffic to be stopped.
- DF: The Dynamic Fragmenter (DF) module is responsible for fragmenting write data to the flash region so that all writes to the flash region are done in 16-bits chunks (a requirement for HyperFlash). It passes all other transaction through unaffected.
- FSS Interfaces:
- MCU_FSS0_OSPI0: The OSPI0 is part of the primary FSS interface (FSS0). It can be configured to use ECC and/or OTFE module.
- MCU_FSS0_OSPI1: The OSPI1 is part of the secondary FSS interface (FSS1). It can be configured with or without ECC.
- MCU_FSS0_HPB0: The HyperBus interface is part of the primary FSS interface (FSS0). It can be configured to use ECC and/or OTFE module.
- FSS I/O Pins:
- OSPI1 I/O Pins: All used MCU_FSS0_OSPI1 interface pins (for more information, see OSPI I/O Signals).
- HyperBus I/O Pins: All used MCU_FSS0_HPB0 interface pins (for more information, see HyperBus I/O Signals).