SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
When regular IBI request appears on the I3C bus, I3C master hardware automatically handles whole IBI procedure based on settings in I3C_SIR_MAP0 through I3C_SIR_MAP5 registers. As the IBI procedure acknowledged by I3C master finishes (including payload reception), host is informed by the IBI interrupt that such event occurred and was successfully processed. At this point, firmware should: