Packet transmission in TR Packet mode involves the following steps:
- The Host allocates and populates a TR packet descriptor. The host will initialize the following fields within the packet descriptor:
- Descriptor Type (set to TR)
- Reload Enable to 1 if looping is required, otherwise 0
- Reload Index to an appropriate offset if Reload Enable set, otherwise 0
- Last Entry to TR count minus 1
- TR Nominal Element Size to a value that is as large as required for any given TR in the buffer
- Packet ID to a value that can be used to correlate the packet when it is placed back on the Tx completion queue
- Source Tag
- Destination Tag (application specific)
- Descriptor reclamation policy fields indicating the mode and queue number for recycling the packet after transmission is complete.
- A set of one or more valid Transfer Request records whose quantity matches the last index specified previously.
- The Host queues the packet onto one of the Transmit Queues for the desired UDMA channel. Channels may provide more than one Tx Queue and may provide a particular prioritization policy between the queues. This behavior is application specific and is controlled by the DMA controller/scheduler implementation.
- The Ring Accelerator provides a level sensitive status signal for the queue which indicates if any packets are currently pending. This level sensitive status line is sent to the hardware block which is responsible for scheduling DMA operations.
- The DMA controller is eventually brought into context for the corresponding Tx channel and begins to process the packet.
- The DMA controller reads the packet descriptor pointer from the RA.
- The DMA controller reads the packet descriptor from memory
- The DMA controller empties the data region in the descriptor by reading the contents in one or more nominal TR sized block data moves. These contents are then transmitted either to an internal UTC (in the case of a UDMA-P) or via PSI-L to a remote UTC (in the case of a UDMA-C).
- If the UDMA includes an internal UTC, all of the data transfers specified in a TR will be completed as a series of reads (for single ended transfers) or reads and corresponding writes (for block copy transfers) and a Transfer Response will be returned indicating the completion and status of the transfer.
- The UDMA will wait until Transfer Responses have been returned for each Transfer Request that it issued. As each Transfer Response is returned, the UDMA will write the response into the TR buffer in the Transfer Response records array. Each response is written into an array index which directly matches the index of the request record to which is corresponds.
- When all Transfer Requests in the packet have been processed and all Transfer Responses have been written back and confirmed to have landed in memory, the UDMA will write the pointer to the packet descriptor to the queue specified in the return queue number fields of the packet descriptor.
- After the Packet Descriptor pointer has been written, the Ring Accelerator indicates the status of the Tx Completion Queues to other ports/processors/prefetcher blocks using events sent to the Interrupt Aggregator. These events are then converted into standard K3 interrupts.