The ECC aggregator generates the following interrupts:
- Correctable interrupt (ECC_SEC_INT) where hardware can correct the error but notifies the system in case of SEC.
- Non-correctable interrupt (ECC_DED_INT) where hardware cannot correct the error in cases of DED, parity check, redundancy check or timeout occurrence.
The following is the sequence for servicing interrupts:
- Software enables the interrupts for an ECC endpoint by writing 0x1 to the corresponding bit of the following interrupt enable registers:
- ECC_SEC_ENABLE_SET_REG0 through
ECC_SEC_ENABLE_SET_REG7 for the correctable interrupt
- ECC_DED_ENABLE_SET_REG0 through
ECC_DED_ENABLE_SET_REG7 for the non-correctable interrupt
- On receiving an interrupt, software checks which ECC endpoint has caused the error by reading the following interrupt status registers:
- ECC_SEC_STATUS_REG0 through ECC_SEC_STATUS_REG7
for the correctable interrupt
- ECC_DED_STATUS_REG0 through ECC_DED_STATUS_REG7
for the non-correctable interrupt
- Software performs serial read operations as described in Section 12.10.4.2.3 to read the following status registers that contain details about the error:
- If the endpoint is ECC RAM:
- ECC_ERR_STAT1
- ECC_ERR_STAT2
- ECC_ERR_STAT3
- If the endpoint is interconnect ECC component:
- ECC_CBASS_ERR_STAT1
- ECC_CBASS_ERR_STAT2
- After the interrupt has been serviced, depending
on the error type, software should clear the corresponding status bits in
the ECC_ERR_STAT1 and ECC_ERR_STAT3 registers or in the ECC_CBASS_ERR_STAT1
register. Software has to poll these registers to guarantee that status bits
are cleared as there is no other indication for write completion over the
ECC serial interface.
The value of the
*_PEND_CLR fields in the ECC_CBASS_ERR_STAT1 register must be read and then
written back to decrement the count of each field back to 0x0. A further
error capture into the ECC_CBASS_ERR_STAT1 register does not occur unless
all its fields are 0x0. The decrement value should not be larger than the
read value. If a field in the ECC_CBASS_ERR_STAT1 register should not be
modified, write a value of 0x0 to that field. - Software writes 0x1 to the corresponding end of interrupt register to clear the interrupt:
- ECC_SEC_EOI_REG for the correctable
interrupt
- ECC_DED_EOI_REG for the non-correctable
interrupt