SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The TS_COMP output is asserted for CPTS_TS_COMP_LEN_REG RCLK periods when the TIME_STAMP[31-0] value compares with the CPTS_TS_COMP_VAL_REG[31-0] and the length value is non-zero. The TS_COMP toggles thereafter on CPTS_TS_COMP_LEN_REG[31-0] RCLK periods. The length high or low can be adjusted by writing the CPTS_TS_COMP_NUDGE_REG[7-0] register value which is a two's complement value. A value of 0xFF will subtract one RCLK from the CPTS_TS_COMP_LEN_REG value. A value of 0x01 will add one RCLK to the CPTS_TS_COMP_LEN_REG value. Only a single high or low time is adjusted (nudged) and the CPTS_TS_COMP_NUDGE_REG value is cleared to zero when the nudge has occurred. The TS_COMP output is asserted low when the CPTS_CONTROL_REG[2] TS_COMP_POLARITY bit is 0.
No compare events and no CPTS_EVNT interrupts are generated in toggle mode.
The CPTS_CONTROL_REG[6] TS_COMP_TOG bit must be set for toggle mode, and must be set before writing a non-zero value to CPTS_TS_COMP_LEN_REG.