SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Figure 12-17 presents the I3C controller block diagram.
The two I3C controllers can be configured in SDR I3C mode or HD-DDR I3C mode. Default operation mode is SDR mode.
Table 12-26 lists the available operation modes.
Operation Mode | Value of I3C_CMD0_FIFO[31] IS_DDR |
---|---|
SDR I3C | 0x0 |
HD-DDR I3C | 0x1 |