SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The MSC supports two independent threads. For this reason, two MSC schedulers are used. Each MSC node scheduler comprises consumer socket and 10 producer sockets. On consumer side, it is either connected to the DMA producer scheduler or the LDC output. On producer socket, it is to the DMA consumer scheduler.
The consumer socket is mapped to:
The producer sockets are mapped to the following output buffers:
Pipeline #n (n = 0, …, 6 configurable) is mapped to this scheduler. When a scheduler is enabled, the DMA producer scheduler triggers UTC data loading from the DDR memory into SL2 memory. Once data is available inside the SL2 meory, the MSC scheduler starts a MSC thread. Prior to starting a MSC thread, the buffer availability to write output data is checked. These consumer and producer sockets can optionally be disabled depending on the usecase.
For both MSC threads, two schedulers are used in VPAC subsystem. Since the MSC core can output maximum 10 scaled outputs (combining MSC0 and MSC1), this fact is utilized in optimizing the DMA consumer sockets and DMA channels required. The need of DMA channels is mutually orthogonal in inverted order, that is, (MSC0-0 and MSC1-9), (MSC0-1 and MSC1-8), etc. are mapped to the same DMA channel. When the MSC needs to run in the same pipeline as LDC, then pipeline number must be same as of the LDC. The consumer socket needs to be connnected to the LDC output (p0).