SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
These flows describe the transfer with FIFO.
The MCSPI module allows the transfer of one or several words, according to different modes:
For all these flows, the host process contains the main process and the interrupt routine. This routine is called on the IRQ signals or by an internal call if the module is used in polling mode.
For more information, see Section 12.1.5.3.6, MCSPI FIFO Buffer Management.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Write MCSPI_IRQSTATUS to reset channel status bits | MCSPI_IRQSTATUS | 1 |
Write MCSPI_IRQENABLE to enable interrupts | MCSPI_IRQENABLE | 1 |
Write MCSPI_CHCONF_0/1/2/3 to configure the channel | MCSPI_CHCONF_0/1/2/3 | 0x- |
Write MCSPI_XFERLEVEL | MCSPI_XFERLEVEL | 0x- |
Start the channel | MCSPI_CHCTRL_0/1/2/3[0] EN | 1 |
IF: Receive only | ||
Wait for the write request (TX empty or DMA write) | ||
Write for the transmitter register with data | MCSPI_TX_0/1/2/3 | 0x- |
ENDIF | ||
Wait for the host event for end of transfer | ||
Stop the channel | MCSPI_CHCTRL_0/1/2/3[0] EN | 0 |