SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Module Clock Input | Description |
---|---|
Clocks | |
R5FSS_CORE0_FCLK | R5FSS_CORE0 functional clock |
R5FSS_CORE0_ICLK | R5FSS_CORE0 interface clock |
R5FSS_CORE1_FCLK | R5FSS_CORE1 functional clock |
R5FSS_CORE1_ICLK | R5FSS_CORE1 interface clock |
Resets | |
Module Reset Input | Description |
R5FSS_CORE0_RST | R5FSS_CORE0 main reset |
R5FSS_CORE0_DBG_RST | R5FSS_CORE0 debug reset (APB excluded) |
R5FSS_CORE1_RST | R5FSS_CORE1 main reset |
R5FSS_CORE1_DBG_RST | R5FSS_CORE1 debug reset (APB excluded) |
Module Interrupt Signal | Description | Type |
---|---|---|
R5FSS_CORE0 Interrupts | ||
R5FSS_CORE0_PMU_0 | R5FSS_CORE0 performance monitor interrupt | Level |
R5FSS_CORE0_VALIRQ_0 | R5FSS_CORE0 validation IRQ interrupt | Level |
R5FSS_CORE0_VALFIQ_0 | R5FSS_CORE0 validation FIQ interrupt | Level |
R5FSS_CORE0_CTI_0 | R5FSS_CORE0 cross trigger interrupt | Level |
R5FSS_COMMON0_COMMRX_LEVEL_0_0 | R5FSS_CORE0 DTRRX full interrupt | Level |
R5FSS_COMMON0_COMMTX_LEVEL_0_0 | R5FSS_CORE0 DTRTX empty interrupt | Level |
R5FSS_CORE0_ECC_CORRECTED_LEVEL_0 | R5FSS_CORE0 SEC ECC interrupt | Level |
R5FSS_CORE0_ECC_UNCORRECTED_LEVEL_0 | R5FSS_CORE0 DED ECC interrupt | Level |
R5FSS_CORE0_EXP_INTR_0 | R5FSS_CORE0 RAT exception interrupt | Level |
R5FSS_COMMON0_ECC_SE_TO_ESM_0_0 | R5FSS_CORE0 ECC single-bit error interrupt (cache and TCM RAMs) | Level |
R5FSS_COMMON0_ECC_DE_TO_ESM_0_0 | R5FSS_CORE0 ECC double-bit error interrupt (cache and TCM RAMs) | Level |
R5FSS_CORE1 Interrupts | ||
R5FSS_CORE1_PMU_0 | R5FSS_CORE1 performance monitor interrupt | Level |
R5FSS_CORE1_VALIRQ_0 | R5FSS_CORE1 validation IRQ interrupt | Level |
R5FSS_CORE1_VALFIQ_0 | R5FSS_CORE1 validation FIQ interrupt | Level |
R5FSS_CORE1_CTI_0 | R5FSS_CORE1 cross trigger interrupt | Level |
R5FSS_COMMON0_COMMRX_LEVEL_1_0 | R5FSS_CORE1 DTRRX full interrupt | Level |
R5FSS_COMMON0_COMMTX_LEVEL_1_0 | R5FSS_CORE1 DTRTX empty interrupt | Level |
R5FSS_CORE1_ECC_CORRECTED_LEVEL_0 | R5FSS_CORE1 SEC ECC interrupt | Level |
R5FSS_CORE1_ECC_UNCORRECTED_LEVEL_0 | R5FSS_CORE1 DED ECC interrupt | Level |
R5FSS_CORE1_EXP_INTR_0 | R5FSS_CORE1 RAT exception interrupt | Level |
R5FSS_COMMON0_ECC_SE_TO_ESM_1_0 | R5FSS_CORE1 ECC single-bit error interrupt (cache and TCM RAMs) | Level |
R5FSS_COMMON0_ECC_DE_TO_ESM_1_0 | R5FSS_CORE1 ECC double-bit error interrupt (cache and TCM RAMs) | Level |
R5FSS_CCMR5 Interrupts | ||
R5FSS_COMMON0_SELFTEST_ERR_PULSE_0 | R5FSS self test failure interrupt | Pulse |
R5FSS_COMMON0_COMPARE_ERR_PULSE_0 | R5FSS CPU bus compare failure interrupt | Pulse |
R5FSS_COMMON0_BUS_MONITOR_ERR_PULSE_0 | R5FSS inactivity monitor failure interrupt | Pulse |
R5FSS_COMMON0_VIM_COMPARE_ERR_PULSE_0 | R5FSS VIM bus compare failure interrupt | Pulse |
R5FSS_CCM_COMPARE_STAT_PULSE_INTR_0 | R5FSS CCMR5 in self test or split mode interrupt | Pulse |
R5FSS_ESM Interrupts | ||
R5FSS_ECC_DE_TO_ESM_0 | R5FSS_CORE0 ESM Interrupt for double bit errors | Level |
R5FSS_ECC_DE_TO_ESM_1 | R5FSS_CORE1 ESM Interrupt for double bit errors | Level |
R5FSS_ECC_SE_TO_ESM_0 | R5FSS_CORE0 ESM Interrupt for single bit errors | Level |
R5FSS_ECC_SE_TO_ESM_1 | R5FSS_CORE1 ESM Interrupt for single bit errors | Level |