SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
If the requests are configured in DMA, write_count and read_count are assigned with ‘N’ when the DMA handlers have completed their ‘N’ CBASS0 accesses.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Start the channel | MCSPI_CHCTRL_0/1/2/3[0] EN | 1 |
Wait for write_count = N AND read_count = N | ||
Stop the channel | MCSPI_CHCTRL_0/1/2/3[0] EN | 0 |
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Read MCSPI_IRQSTATUS | MCSPI_IRQSTATUS | 0x- |
Write MCSPI_IRQSTATUS to reset channel status bits | MCSPI_IRQSTATUS[channel i bits] | 0b1111 |
IF: TXx_EMPTY | ||
Write the transmitter register with data | MCSPI_TX_0/1/2/3 | 0x- |
Increment write_count +1 | ||
IF: RXx_FULL | ||
Read the receiver register | MCSPI_RX_0/1/2/3 | |
Increment read_count +1 | ||
ENDIF |