SPRUJ28 User guide

SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

10.2.3.2.1 Block Diagram

Figure 6-152 shows UDMA main internal components.

Figure 10-17 UDMA Block-Diagram

Bus Interface Unit

The Bus Interface Unit (BIU) is responsible for merging and buffering all of the transactions that originate from the various master blocks inside the DMA controller into the 4 separate VBUSM master interfaces. Arbitration between the blocks to a given VBUSM interface is round robin within a single priority level. A two word deep retiming buffer is provided on each sub interface of each provided VBUSM bus.

Tx Prefetcher Configuration Registers

The Tx Prefetcher Configuration Registers block is responsible for providing memory mapped registers for configuration of the Tx DMA function, monitoring the fullness level of the Tx prefetch buffers, maintaining Tx prefetch state information, arbitrating which channel will be allowed to perform prefetch work next, issuing scheduler commands to the Tx Prefetch Units, and writing back the updated state returned from those same prefetch units.

Tx Prefetch Unit(s)

The Tx Prefetch Unit block is responsible for performing a fetch of either a Packet Descriptor (packet mode) or a TR to feed the downstream Tx DMA/Tx Read Units.

Tx Configuration Registers

The Tx Configuration Registers block (UDMASS_UDMAP0_CFG_TCHAN Registers) is responsible for monitoring the fullness level of the Tx Per Channel FIFOs, monitoring data transfer work which is pending, maintaining data movement thread state information, arbitrating which channel will be allowed to perform work next, issuing scheduler commands to the Tx Packet and TR based DMA core blocks, and writing back the updated state returned from those same DMA core blocks.

Tx Packet DMA Unit

The Tx Packet DMA Unit block implements all of the state machine functionality necessary to implement the K3 DMA Host and Monolithic Tx protocol. The Tx Packet DMA unit initiates VBUSM transactions in order to read and write descriptor pointers from the Ring Accelerator, read descriptors from memory, and read data from buffers in memory.

Tx Packet Coherency Unit

The Tx Packet Coherency Unit is responsible for ensuring that all control structures and data have been read (and updated if applicable) by the Tx DMA unit(s) prior to returning the packet descriptor pointer to the appropriate return queue in the Ring Accelerator. This unit ensures that the ordering of the Packet Descriptor pointer writes to the return queue directly matches the ordering in which those packets were fetched from the Tx queue. This unit is only used on channels which are in Pass-By-Reference mode

Tx TR Coherency Unit

The Tx TR Coherency Unit is responsible for ensuring that all control structures and data have been read prior to allowing the TR response to be written to either the Packet Descriptor or a Pass by Value queue in the Ring Accelerator. This unit ensures that the ordering of TR response writes also directly matches the ordering of Transfer Requests that were processed by the channel. This unit is only used on channels which are in TR mode.

Tx External Channel TR Coherency Unit

The Tx External Channel TR Coherency Unit is responsible for ensuring that TRs received back from remote UTCs are written in strong order to either the Packet Descriptor or a Pass-by-Value queue in the Ring Accelerator. This unit is only used on external UTC channels.

Tx Event Coherency Unit

The Tx Event Coherency Unit is responsible for ensuring that all data transfers have completed before a completion event is issued through the outgoing Event Transport Lane (ETL). This unit is only used on channels which are in TR mode.

Tx Per Channel Buffers

The Tx Per Channel Buffers implement a FIFO for each Tx DMA channel that is used for buffering packet control and payload data that has been fetched by the Tx Packet DMA units or Tx Third Party Read unit modules. The buffers are byte oriented on write so that the data from the DMA units which may not be full words can be packed properly. The buffers are block oriented on read in accordance with the transport mechanism outlined in the PSI-L Interface specification. Each Tx (source) channel in the UDMA controller maps directly onto a thread in the Tx PSI-L interface. The Tx Per Channel Buffer block outputs queue fullness information to the Tx Scheduler block which it then uses to determine when it must initiate DMA opportunities to backfill the buffers. The Tx Per Channel Buffer will initiate transfers to the remote paired thread whenever any data is available in each channel buffer and credits are available in the corresponding thread. The block will simultaneously monitor the status of all of the threads and will perform a round robin arbitration between the different threads for the use of the Transmit PSI-L interface. Each thread for which the target is indicating it can accept data and which currently has data available in the channel buffer will be included in the arbitration.

Rx FlowID Firewall

The Rx FlowID firewall checks the incoming flowID on the received packet from the Rx PSI-L interface to verify that it is either the corresponding flowID for the channel (that is, the default flow ID for the channel which is the same as the channel number) or that the flowID falls within a programmed range that is considered legal for the channel. If the received flowID does not fall within the legal range then the packet is dropped and the error is trapped.

Rx Per Channel Buffers

The Rx Per Channel Buffers implement a FIFO for each Rx DMA channel that is used for buffering packet control and payload data that has been pushed into the DMA from the Rx PSI-L interface. The Rx Per Channel Buffers also includes an arbitration unit which determines which Rx DMA channel must be serviced next

Rx Configuration Registers

The Rx Configuration Registers block (UDMASS_UDMAP0_CFG_RCHAN Registers) is responsible for providing memory mapped registers for configuration of the Rx DMA functions including the default settings for the free descriptor and destination queues. For modularity and high speed pipelining reasons, the Rx traffic is looped through the Rx Configuration Registers block where the original stream information is merged with information from the configuration registers on its way to the Rx DMA unit module. This prevents the Rx DMA Core from having to spend cycles accessing the channel configuration information for the channel.

Rx Packet DMA Unit

The Rx Packet DMA Unit block implements all of the state machine functionality necessary to implement the K3 DMA Rx protocol for Host and Monolithic descriptor types. The Rx Packet DMA Unit initiates VBUSM transactions in order to read descriptor pointers from the Ring Accelerator, read buffer descriptor information, write descriptors to memory, and write data to buffers in memory.

Rx Packet Coherency Unit

The Rx Packet Coherency Unit is responsible for ensuring that all control structures and data have been written by the Rx DMA unit(s) prior to returning the packet descriptor pointer to the appropriate return queue in the Ring Accelerator. This unit ensures that the ordering of the Packet Descriptor pointer writes to the return queue directly matches the ordering in which those packets were fetched from the Rx free queues. Writes are not considered complete by this unit until the entire write status has been returned for all outstanding transactions for a given packet ID. This unit is only used on channels which are in Pass By Reference mode

Rx TR Coherency Unit

The Rx TR Coherency Unit is responsible for ensuring that all control structures have been read and all data has been written prior to allowing the TR response to be written to either the Packet Descriptor or a Pass by Value queue in the Ring Accelerator. This unit ensures that the ordering of TR response writes also directly matches the ordering of Transfer Requests that were processed by the channel. This unit is only used on channels which are in TR mode.

Rx Event Coherency Unit

The Rx Event Coherency Unit is responsible for ensuring that all data transfers have completed before a completion event is issued through the outgoing ETL. This unit is only used on channels which are in TR mode.

Third Party Read Unit

The Third Party Read Unit(s) are responsible for sequencing all of the Tx side channel control and data transfers. The Third Party Read Unit is responsible for performing the actual data read operations including sequential address generation and nested loop control. Like the Tx Packet DMA Unit, the Third Party Read Unit receives state information from the Tx Configuration Registers and returns that state when a transfer opportunity is complete. The Third Party Read Unit will perform as much data transfer as is specified in the Transfer Request up until either a fixed number of bytes have been transferred, the transfer is completed, or the transfer has reached a point which requires an input trigger event to proceed.

Third Party Write Unit

The Third Party Write Unit(s) are responsible for sequencing all of the Rx side channel data transfers. The Third Party Write Unit is responsible for performing the actual data write operations including sequential address generation and nested loop control. Like the Rx Packet DMA Unit, the Third Party Write Unit receives state information from the Rx Configuration Registers and returns that state when a transfer opportunity is complete. The Third Party Write Unit will perform as much data transfer as is specified in the Transfer Request up until either a fixed number of bytes have been transferred or the transfer is completed or the transfer has reached a point which requires an input trigger event to proceed.

Event Handler

The Event Handler block is responsible for accepting and logging channel triggering events and for generating channel completion and error events.

PSI-L Real Time Proxy

The PSI-L Real Time Proxy block is responsible for allowing tunneled VBUSP transactions to the Real Time Remote Peer registers to generate PSI-L configuration transactions to the paired remote peer for each Tx and Rx channel.