At any given time the PDMA can be in one of three different states as follows:
- INIT: This is the initial state of the machine
during and immediately after reset. During this state, all of the RAMs inside
the PDMA will be initialized to known values including the ECC redundant parity
bits. While in the INIT state, the DMA will de-assert all 'ready' signals on all
applicable target
interfaces and will de-assert all 'request' signals on all applicable controller interfaces. The
PDMA will automatically transition out of the INIT state into the IDLE state
when all of the RAM initialization has been completed.
- IDLE: Once the PDMA leaves the INIT state, it
enters the IDLE state whenever no outstanding transactions are pending on any of
the PDMA interfaces (controller or target). The IDLE state is generally a transient state and is used by
the PDMA to determine when it is appropriate to allow the SoC power management
complex to turn off the clock. As channels have work queued on them and
transactions begin flowing into the system, the PDMA transitions to the ACTIVE
state. When no more work is pending, or when the host pauses/disables active
channels, or when the power management complex on the SoC desires to shut down
the PDMA and asserts 'clock stop request', the PDMA will account for any
outstanding transactions and will re-enter the IDLE state. The PDMA leaves the
IDLE state anytime it generates or receives a transactions that requires a
return response as those protocols dictate that the clock must remain running to
avoid faulting the handshaking protocol.
- ACTIVE: The PDMA enters the ACTIVE state as soon as it issues a transaction or receives a transaction on any interface that uses a split protocol (expects a later response for a request). When all transactions have been accounted for (responses have all been either received or sent), the PDMA transitions to the IDLE state.