SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Additional integration details for the ePWM modules on J7AEP and J7AHP are detailed in the following sections.
ePWM SynchronizationThe ePWM SYNCI inputs allow the timebase (TBCNT) of an ePWM module to be synchronized with another epWM module or other event. This allows the addition of lead/lag phase control to waveforms generated by the other ePWM module. On J7AEP/J7AHP, ePWM[2:0] SYNCI inputs are daisy-chained together to allow synchronization to each other or to an external SYNCI input pin. The ePWM[5:3] SYNCI inputs are also daisy-chained together and may be synchronized to a separate external SYNCI input pin , or to ePWM[2:0] as shown below:
ePWM SOC Outputs
The ePWM modules provide Start of Conversion (SOCA, SOCB) events that can be used to trigger the on-chip ADCs or off-chip modules. On J7AEP/J7AHP, the SOCA and SOCB events from each ePWM module are ORed together allowing any of the 6 ePWMS to act as the SOCA or SOCB event generator:
ePWM Tripzone
Each ePWM supports 6 tripzone event inputs. On J7AEP/J7AHP, each tripzone input to all six ePWM modules are tied to a common TZn input pin allowing any ePWM trip event to be triggered by any of the six input pins.
ePWM Timebase Clock Synchronization
The ePWM modules include a timebase counter for pre-scaling the input clock to generate the TBCLK (timebase clock) used to clock the PWM. The timebase counter is enabled via the ePWM TBCLKEN input. This input is driven (high) through the associated CTRL_MMR0 PWMn_CTRL_tb_clken register bit (where n is the ePWM instance). In order for multiple ePWM module timebase counters to be started synchronously, the TBCLKEN inputs can also be driven by the CTRL_MMR0 SUP_CTRL7_epwmn_tb_clken bits. Using the SUP_CTRL7 register allows multiple ePWM TBCLKEN inputs to be enabled with a single register write. The two tb_clken sources are ORed together so that setting the bit in either location will enable the associated ePWM’s timebase counter: