SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
This section describes the HyperBus external connections (environment).
Table 12-155 describes the HyperBus I/O signals.
Module Pin | I/O(1) | Description |
---|---|---|
CK | O | HyperBus Clock Output (differential) |
CKn | O | HyperBus Inverted Clock Output (differential) |
RWDS | I/O/HiZ | HyperBus Read/Write Data Strobe |
DQ[7:0] | I/O/HiZ | HyperBus Data |
CSn0 | O | HyperBus Chip Select 0 |
CSn1 | O | HyperBus Chip Select 1 |
RESETn | O | HyperBus Reset Output |
RESETOn | I | Reset State Indicator (output from HyperBus memory) |
INTn | I | Memory Interrupt (output from HyperBus memory) |
WPn(2) | O | HyperBus Write Protect (output to HyperBus memory) |