SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The host initiates a channel pause by setting the PDMA_PSILCFG_RX_RT_ENABLE[29] PAUSE bit. The paused channel can be resumed by clearing the register bit.