SPRUJ28 User guide

SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

5.4.6.2 Oscillator Clock Loss Detection

The device supports WKUP_HFOSC0 clock loss circuitry to detect when WKUP_HFOSC0_CLK stops toggling. If CTRLMMR_WKUP_MCU_PLL_CLKSEL[8] CLKLOSS_SWTCH_EN is set and WKUP_HFOSC0_CLK stops toggling condition is detected, the reference clock is switched from WKUP_HFOSC0_CLKOUT to WKUP_CLK_12M_RC to allow the device to operate with a slower clock. The WKUP_HFOSC0_CLK stops toggling condition is reported as an error to WKUP_ESM0 regardless of the value of CTRLMMR_WKUP_MCU_PLL_CLKSEL[8] CLKLOSS_SWTCH_EN. Integration diagram of WKUP_HFOSC0 clock loss detection is presented in Figure 5-14.

Figure 5-14 WKUP_HFOSC0 Clock Loss Detection Integration Diagram

WKUP_ESM0 can optionally generate an interrupt to WKUP_DMSC0 and MCU_R5FSS so they can save some critical contents such as error logging to scratch pad memory or external flash. ESM must also be configured to report this error on the SAFETY_ERRORn pin.

WKUP_HFOSC0 clock loss is a catastrophic failure since this clock is the most critical system clock. During the clock loss condition an external system intervention is required.

The clock loss mux is not a glitch free mux. The mux control is synchronized to the CLK_12M_RC clock. Since WKUP_HFOSC0_CLK has stopped switching the mux should transition to RC Clock without producing glitches.

Hence it is important to ensure that MCU_SAFETY_ERRORn is pulled low during this error condition. In clock-loss condition, the device reports the error to the external device through MCU_SAFETY_ERRORn pin - the pin is driven Low. The recovery mechanism is up to the external system (such as a PMIC to take action). For example, it can try a full system power cycle to see if the system recovers. If the system does not recover then, it has to take some other action such as to check system clocks, external crystal, supply rails.

PLL will lose the lock when clock loss is detected. During this time 12.5-MHz RC clock is output through the bypass muxes. The PLL will relock to a new frequency based on 12.5 MHz.

In an event of clock glitch which may potentially hang the device, then the WKUP_DMSC0 watchdog timer will expire and will generate an internal reset for the whole device.