SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The CIR function generates interrupts that can be enabled and disabled by writing to the appropriate bit in the interrupt enable register (UART_IER_CIR). The interrupt status of the device can be checked by reading the interrupt identification register (UART_IIR_CIR).
The UART, IrDA, and CIR modes have different interrupts in the UART module and, therefore, different UART_IER_CIR and UART_IIR_CIR mappings, depending on the selected mode.
Table 12-75 lists the interrupt modes to be maintained. In CIR mode, the sole purpose of the UART_IIR_CIR[5] TX_STATUS_IT bit is to indicate that the last bit of infrared data was passed to the TX pin.
IIR_CIR Bit Number | Interrupt Type | Interrupt Source | Interrupt Reset Method |
---|---|---|---|
0 | |||
1 | THR interrupt | TFE (THR empty) (FIFO disabled) TX FIFO below trigger level (FIFO enabled) | Write to the UART_THR register until the interrupt condition disappears |
2 | |||
3 | |||
4 | N/A for CIR mode | N/A for CIR mode | N/A for CIR mode |
5 | TX status | Transmission of the last bit of the frame is complete successfully | Read the UART_IIR_CIR register |
6 | N/A for CIR mode | N/A for CIR mode | N/A for CIR mode |
7 | N/A for CIR mode | N/A for CIR mode | N/A for CIR mode |