SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
CAC correction requires remapping locations of Red and Blue pixels to align with Green pixel. Green pixel is taken as reference and assumed no correction is needed on Green pixel. Legacy block based correction wouldn’t fit into the streaming VISS pipe line and incurs additional bandwidth and latency. CAC HWA is implemented using line based back mapping architecture. Correction involves back-mapping each output pixel to pixel position in the source image, and thus the corrected image is fully populated. As the back mapped pixel locations mostly fall onto fractional coordinates, correction involves bi-cubic interpolation among the nearest available pixels.
As shown in Figure 6-80, CAC consists of Timing control module, 8KB LUT with mesh correction offset table, Mesh LUT bi-linear interpolation block, Pixel interface module, pixel bi-cubic interpolation block and 10 pixel line memories.
Timing Control module handles all the timing synchronization aspects of CAC. It generates the Output frame co-ordinates, initiates the Mesh LUT operation on receiving 7th input valid line. It also handles timing synchronization between all the blocks in the design.