All filters enabled for a multi-scaling thread are programmed via:
- VPAC_MSC_CORE_CFG_j[0] FILTER_MODE; Coefficient
Set Selection - VPAC_MSC_CORE_CFG_j[3-2] HS_COEF_SEL, VPAC_MSC_CORE_CFG_j[5-4]
VS_COEF_SEL, VPAC_MSC_CORE_CFG_j[10-7] SP_HS_COEF_SEL,
VPAC_MSC_CORE_CFG_j[15-12] SP_VS_COEF_SEL; and filter tap size parameters
VPAC_MSC_CORE_CFG_j[11] SP_VS_COEF_SRC and VPAC_MSC_CORE_CFG_j[6]
SP_HS_COEF_SRC.
- Coefficients set in VPAC_MSC_CORE_C210_j,
VPAC_MSC_CORE_C43_j, VPAC_MSC_CORE_C210_j_k, VPAC_MSC_CORE_C43_j_k
registers.
- ROI source offset -
VPAC_MSC_CORE_SRC_ROI_j[28-16] Y_OFFSET and VPAC_MSC_CORE_SRC_ROI_j[12-0]
X_OFFSET, and size. The size of ROI depends on the X and Y offsets. For
full-size set the offsets to 0. Note that the ROI_SIZE may or may not be same as
the MSC frame size (set in MSC_FRAME_SIZE_j[28-16] HEIGHT and
MSC_FRAME_SIZE_j[12-0] WIDTH) - depending on whether ROI is full or sub-frame
sized.
- Output size - VPAC_MSC_CORE_OUT_SIZE_j[28-16]
HEIGHT and VPAC_MSC_CORE_OUT_SIZE_j[12-0] WIDTH.
- Filter parameters - VPAC_MSC_CORE_FIRINC_j[14-0]
HS, VPAC_MSC_CORE_FIRINC_j[30-16] VS, VPAC_MSC_CORE_ACC_INIT_j[27-16] VS, and
VPAC_MSC_CORE_ACC_INIT_j[11-0] HS.
Filter thread mapping is done with output channel configuration parameters (MSC_BUF_CFG_j[7] THREAD_MAP). Specifying the mapping in one register for each channel prevents any resource conflict.