The SoC has many peripherals and a large number of event sources (interrupt, time sync or DMA). The use of events is completely dependent on a user's specific application, which drives a need for maximum flexibility in which event sources are used in the system. It is also completely up to software control as to how the events are serviced.
The SoC includes the following interrupt servicing modules (hosts):
- Security Management Subsystem (WKUP_SMS0):
- 2 Arm Cortex-M4F
cores
- 2 Nested vectored
interrupt controller (NVIC)
- Compute cluster:
- Three
processor subsystems:
- Dual-core
Arm Cortex-A72 microprocessor unit (A72SS0)
- 2 Single-core C71x DSP
subsystems (C71SS0, C71SS1)
- Two interrupt controllers, both integrated inside the MSMC wrapper:
- Arm generic interrupt controller (GIC-500)
supports both cores
in the dual-A72 cluster
- Cluster level event controller (CLEC) supports
the C71x DSPs
- Microcontroller units (R5FSS0, R5FSS1, MCU_R5FSS0), each
implementing:
- Two Arm Cortex-R5F
cores
- Vectored interrupt
manager (VIM)
Most of the system events are routed directly to the various proccesing elements but in some cases it is impractical to route all events of a certain group (for example, GPIO events) to each processing element. For this purpose, the SoC integrates several interrupt router (INTRTR) instances. Each interrupt router aggregates a number of system events and can route each event to a given processing element by using simple combinational logic (a set of multiplexors). Event selection is controlled through the associated registers within each interrupt router.
The following interrupt router instances are part of the SoC interrupt architecture:
- WKUP domain GPIO interrupt router (WKUP_GPIOMUX_INTRTR0):
- Provides selection of active module interrupts
for the WKUP_GPIOx modules
- MAIN domain GPIO interrupt router (GPIOMUX_INTRTR0):
- Provides selection of active module interrupts
for the MAIN domain GPIOx modules
- MAIN-to-MCU domain level interrupt router (MAIN2MCU_LVL_INTRTR0):
- Provides selection of active MAIN domain module level interrupts for routing to MCU domain processing elements
- Reduces the number of event voltage domain crossings
- MAIN-to-MCU domain pulse interrupt router (MAIN2MCU_PLS_INTRTR0):
- Provides selection of active MAIN domain module pulse interrupts for routing to MCU domain processing elements
- Reduces the number of event voltage domain crossings
In addition, the following interrupt router instances are part of the SoC time sync architecture:
- Time sync event router (TIMESYNC_INTRTR0):
- Provides selection of active common platform time synchronization (CPTS) events for routing to CPTS capable modules
- Compare event router (CMPEVT_INTRTR0):
- Provides selection of active CPTS counter compare events for routing as processor interrupts or DMA events
For more details on time sync routers, see Time
Sync Routers.