SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
This section describes PCIe subsystem ports related to clocks, resets, and hardware requests.
| Clocks | |
| Module Clock Input | Description |
| PCIE_FICLK | PCIE interface bus clock (CBA_CLK). |
| PCIE_PM_CLK | PCIE core free-running clock used for low power state transitions and clock control generation. |
| PCIE_CPTS_RCLK | PCIE CPTS reference clock (RCLK). The CPTS RCLK clock frequency should be greater than or equal to the PCIE CBA_CLK clock frequency. Otherwise, the software will have to add some wait cycles before a correct event is generated by the CPTS module. Additionally, the CPTS RCLK should be set to same frequency as the PCIe core clock. |
| PCIE_LANE0_TXMCLK | PCIE core clock (CORE_CLK)
driven by SERDES via lane 0. In multi-lane modes, only PCIE1_LANE0_TXMCLK is used as the core clock input for all lanes. The TXMCLKs for the rest of the lanes are left unconnected |
| PCIE_LANE0_RXCLK | PCIE PIPE interface clock
driven by SERDES via lane 0. In multi-lane modes, only PCIE1_LANE0_RXCLK is used as the PIPE interface clock for all lanes. The RXCLKs for the rest of the lanes are left unconnected. |
| SERDES0_IP2_LN0_TXCLK | PCIE lane 0 PIPE/RAW TX return clock. |
| SERDES0_IP2_LN1_TXCLK | PCIE lane 1 PIPE/RAW TX return clock. |
| SERDES0_IP2_LN2_TXCLK | PCIE lane 2 PIPE/RAW TX return clock. |
| SERDES0_IP2_LN3_TXCLK | PCIE lane 3 PIPE/RAW TX return clock. |
| Resets | |
| Module Reset Input | Description |
| PCIE_RST | PCIE reset |
| Interrupt Requests | ||
| Module Interrupt Signal | Description | Type |
| PCIE_DOWNSTREAM_PULSE_0 | PCIE downstream interrupt | Pulse |
| PCIE_ERROR_PULSE_0 | PCIE error interrupt | Pulse |
| PCIE_FLR_PULSE_0 | PCIE function level interrupt | Pulse |
| PCIE_HOT_RESET_PULSE_0 | PCIE hot reset interrupt | Pulse |
| PCIE_LEGACY_PULSE_0 | PCIE legacy interrupt | Pulse |
| PCIE_LINK_STATE_PULSE_0 | PCIE link state interrupt | Pulse |
| PCIE_LOCAL_LEVEL_0 | PCIE local interrupt | Level |
| PCIE_PWR_STATE_PULSE_0 | PCIE power state interrupt | Pulse |
| PCIE_PHY_LEVEL_0 | PCIE PHY interrupt | Level |
| PCIE_PTM_VALID_PULSE_0 | PCIE PTM valid interrupt | Pulse |
| PCIE_ECC0_CORR_LEVEL_0 | PCIE ECC AGGR 0 correctable error interrupt | Level |
| PCIE_ECC0_UNCORR_LEVEL_0 | PCIE ECC AGGR 0 uncorrectable error interrupt | Level |
| PCIE_ECC1_UNCORR_LEVEL_0 | PCIE ECC AGGR 1 uncorrectable error interrupt | Level |
| PCIE_ASF_NONFATAL_LEVEL_0 | PCIE active internal diagnostics interrupt | Level |
| PCIE_ASF_FATAL_LEVEL_0 | PCIE active internal diagnostics interrupt | Level |
| PCIE_CPTS_PEND_0 | PCIE timesync interrupt | Level |
| PCIE_DPA_PULSE_0 | PCIE dynamic power allocation interrupt | Pulse |
| DMA Events | ||
| Module DMA Event | Description | Type |
| - | The PCIe subsystem does not provide built-in DMA capabilities | - |
| Time Sync and Compare Events (Output) | ||
| Module Event | Description | Type |
| PCIE_CPTS_HW1_PUSH_0 | PCIE CPTS hardware push event (HW1_TS_PUSH) | Edge |
| PCIE_CPTS_COMP_0 | PCIE CPTS compare output interrupt | Edge |
| PCIE_CPTS_SYNC_0 | PCIE CPTS sync output interrupt | Edge |
| PCIE_CPTS_GENF_0 | PCIE CPTS GENF0 output interrupt | Edge |
| Time Sync Events (Input) | ||
| Module Event | Description | Type |
| PCIE_CPTS_HW2_PUSH_0 | PCIE CPTS hardware time stamp push event (HW2_TS_PUSH) | Edge |